MICROCOMPUTER
MN101C00
MN101C115/117 LSI User's Manual
Pub. No. 21411-011E
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PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names,logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations.
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Request for your special attention and precautions in using the technical information and semiconductors described in this book
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign Trade Control Law" is to be exported or taken out of Japan. The contents of this book are subject to change without notice in matters of improved function. When finalizing your design,therefore,ask for the most up-to-date version in advance in order to check for any changes. We are not liable for any damage arising out of the use of the contents of this book, or for any infringement of patents or any other rights owned by a third party. No part of this book may be reprinted or reproduced by any means without written permission from our company. This book deals with standard specifications. Ask for the latest individual Product Standards or Specifications in advance for more detailed information required for your design,purchasing and applications.
(2)
(3)
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(5)
If you have any inquiries or questions about this book or our semiconductors, please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales Department.
How to Read This Manual
The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as well as a Mask ROM version is available so users can write a program by themselves.
ROM 8K 16K 16K MN101C115*1 MN101C117 MN101CP117
RAM 256 512 512
*1 :
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Unit Byte
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s Organization
In this LSI manual, the MN101C117 functions are presented in the following order: overview, CPU basic functions, port functions, timer functions, serial functions, and other peripheral hardware functions.
How to Read This Manual-1
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s Manual Configuration
Each section of this manual consists of a title, summary, main text, supplemental information, precautions and warnings. The layout and definition of each section are shown below.
Chapter 4 Timer Functions
Subtitle Sub-subtitle
The smallest block in this manual. 4-3 16-bit Timer Operation (timer 4)
Summary
4-3-1 Overview
Introduction to the section.
Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin. An input capture function and added pulse PWM output function can also be used.
Main text
s Timer Operation Settings for timer operation are listed below. (1) (2) (3) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count operation of timer 4 is stopped. Set the TM4CK2~0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is selected.
When servicing an interrupt, reset the timer 4 interrupt request flag before operating timer 4. During a count operation, be careful if the value set in TM4OCH and TM4OCL is smaller than the value of binary counter 4, since the count-up operation will continue until overflow occurs.
Supplementary information
Supplementary information for the main text. An explanation of terminology is also included.
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Clock
TM4EN
Write to registers TM4OCH, TM4OCL
Binary counter 4
04
05
06
07
08
09
00
Key information
Important information from the text.
Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing
Precautions and warnings
Precautions are listed in case of lost functionality or damage. Be sure to read.
16-bit Timer Operation (timer 4)
If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented. If the value of TM4OCH and TM4OCL registers is overwritten while timer 4 has stopped counting, binary counter 4 will be reset to X'0000'.
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How to Read This Manual-2
s Finding Desired Information
This manual provides four methods for finding desired information quickly and easily. (1) (2) (3) (4) Consult the index at the front of the manual to locate the beginning of each section. Consult the table of contents at the front of the manual to locate desired titles. Consult the list of figures at the front of the manual to locate illustrations and charts by title name. Chapter names are located at the top outer corner of each page, and section titles are located at the bottom outer corner of each page.
s Related Manuals
The following manuals are also available from Panasonic as part of the MN101C00 series. MN101C00 Series LSI Manual MN101C00 Series Command Manual MN101C00 Series Cross Assembler User's Manual MN101C00 Series C Compiler User's Manual Operation MN101C00 Series C Compiler User's Manual Language MN101C00 Series C Compiler User's Manual Library MN101C00 Series C Source Code Debugger User's Manual MN101C00 Series PanaX Series Installation Manual
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s Where to Send Inquires
Please send any inquires or questions concerning the contents of this manual to the Panasonic semiconductor design center closest to you. A list of addresses is provided at the end of this manual for your convenience.
How to Read This Manual-3
Contents
Chapter 1
Overview
Chapter 2
Basic CPU Functions
Chapter 3
Port Functions
Chapter 4
Timer Functions
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Chapter 5
Serial Functions
Chapter 6
A/D Conversion Functions AC Zero-Cross Circuit/Noise Filter
Chapter 7
Appendices
0 1 2 3 4 5 6 7 8
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Contents
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Contents
Chapter 1
1-1-1 1-1-2
Overview
Overview ..........................................................................................................2 Product Summary .............................................................................................2
1-1 Product Overview...........................................................................................................2
1-2 Hardware Functions .......................................................................................................3 1-3 Pins .................................................................................................................................5 1-3-1 1-3-2 1-4-1 1-5-1 1-5-2
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Pin Diagram......................................................................................................5 Pin Function Summary .....................................................................................8 Block Diagram................................................................................................12 Absolute Maximum Ratings...........................................................................13 Operating Conditions......................................................................................14 DC Characteristics .........................................................................................17 A/D Converter Characteristics........................................................................21 ROM Option ...................................................................................................22 Option Check List...........................................................................................23
1-4 Overview of Functions .................................................................................................12 1-5 Electrical Characteristics..............................................................................................13
1-5-3 1-5-4 1-6-1 1-6-2
1-6 Option...........................................................................................................................22
1-7 Outline Drawings .........................................................................................................24
Chapter 2
Basic CPU Functions
2-1 Overview ......................................................................................................................28 2-2 Address Space 2-2-1 2-2-2 2-3-1 2-3-2 2-4-1 2-4-2 2-4-3 Memory Configuration ...................................................................................28 Special Function Registers .............................................................................28 Overview .......................................................................................................30 Control Register..............................................................................................30 Accepting and Returning from Interrupts.......................................................31 Interrupt Sources and Vector Addresses .........................................................33 Interrupt Control Registers .............................................................................34
2-3 Bus Interface ................................................................................................................29
2-4 Interrupts ......................................................................................................................31
2-5 Reset .............................................................................................................................36
Chapter 3 Port Functions
3-1 Overview ......................................................................................................................38 3-2 Port Control Registers ..................................................................................................41 3-2-1 3-2-2 Overview ........................................................................................................41 I/O Port Control Registers ..............................................................................45
3-3 I/O Port Configuration and Functions..........................................................................47
Chapter 4 Timer Functions
4-1 Overview ......................................................................................................................56 4-2 8-bit Timer Operation (timers 2, 3) ..............................................................................62 4-2-1 4-2-2
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Overview ........................................................................................................62 Operation ........................................................................................................63 Overview ........................................................................................................69 Operation ........................................................................................................69 Overview ........................................................................................................76 Operation ........................................................................................................76 Overview ........................................................................................................77 Operation ........................................................................................................77 Overview ........................................................................................................78 Setup and Operation .......................................................................................78 Overview ........................................................................................................79 Setup and Operation .......................................................................................79 Buzzer Output Setup and Operation ...............................................................80
4-3 16-bit Timer Operation (timer 4)..................................................................................69 4-3-1 4-3-2 4-4-1 4-4-2 4-5-1 4-5-2 4-6-1 4-6-2 4-7-1 4-7-2 4-8-1
4-4 8-bit Timer Operation (timer 5)....................................................................................76
4-5 Time Base Operation....................................................................................................77
4-6 Watchdog Timer Operation ..........................................................................................78
4-7 Remote Control Output Operation ...............................................................................79
4-8 Buzzer Output ..............................................................................................................80 4-9 Timer Function Control Registers................................................................................81 4-9-1 4-9-2 4-9-3 4-9-4 Overview ........................................................................................................81 Programmable Timer/Counters ......................................................................82 Timer Mode Registers ....................................................................................85 Timer Control Registers .................................................................................89
Chapter 5 Serial Functions
5-1 Overview ......................................................................................................................92 5-2 Synchronous Serial Interface .......................................................................................94 5-2-1 5-2-2 5-2-3 5-3-1 5-3-2 5-3-3 5-4-1 5-4-2 5-4-3 5-4-4 Overview ........................................................................................................94 Setup and Operation .......................................................................................94 Serial Interface Transfer Timing.....................................................................99 Overview ......................................................................................................101 Setup and Operation .....................................................................................101 How to Use the Baud Rate Timer.................................................................105 Overview ......................................................................................................106 Transmit/Receive Shift Registers, Receive Data Buffer ..............................107 Serial Interface Mode Registers ...................................................................108 Serial Interface Control Register ..................................................................112
5-3 Half-duplex UART Serial Interface ...........................................................................101
5-4 Serial Interface Control Registers ..............................................................................106
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Chapter 6 A/D Conversion Functions
6-1 Overview ....................................................................................................................114 6-2 A/D Conversion..........................................................................................................115 6-3 A/D Converter Control Registers ...............................................................................117 6-3-1 6-3-2 6-3-3 Overview.......................................................................................................117 A/D Control Register (ANCTR)...................................................................118 A/D Buffers (ANBUF) .................................................................................120
Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-1 Overview ....................................................................................................................122 7-2 AC Zero-Cross Circuit Operation ..............................................................................123 7-2-1 7-3-1 7-3-2 7-4-1 7-4-2 Setup and Operation .....................................................................................123 Overview ......................................................................................................124 Example Input and Output Waveforms for Noise Filter...............................125 Overview ......................................................................................................126 Noise Filter Control Register (NFCTR) .......................................................127 7-3 Noise Filter.................................................................................................................124
7-4 AC Zero-Cross Control Register................................................................................126
Appendices
8-1 EPROM Versions .......................................................................................................130 8-1-1 8-1-2 8-1-3 8-1-4 8-1-5 8-1-6 8-1-7 8-1-8 Overview ......................................................................................................130 Cautions on Use............................................................................................131 Erasing Written Data in Windowed Packages ..............................................132 (PX-AP101C11-SDC, PX-AP101C11-FBC) Characteristics of EPROM Versions.............................................................133 Writing to Internal EPROM..........................................................................134 Cautions on Handling the ROM Writer........................................................136 Option Bit .....................................................................................................137 Writing Adapter Connection.........................................................................138
8-2 Instruction Sets...........................................................................................................141 8-3 Instruction Maps.........................................................................................................147
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8-4 Special Function Registers .........................................................................................149
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Chapter 1
Overview
1
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1
Chapter 1 Overview
1-1 Product Overview
1-1-1 Overview
The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of peripheral functions. This chip series is well suited for VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, remote control, fax machine, musical instrument, and other applications. The MN101C117 has an internal 16 KB of ROM and 512 bytes of RAM. Peripheral functions include four sets of timers, one set of serial interfaces, an A/D converter, and remote control output. The configuration of this microcomputer is well suited for applications as a system controller in a VCR selection timer, CD player, MD, or portable terminal. With two oscillation systems (max. 20 MHz/32 kHz) contained on the chip of 48-pin QFP package, the system clock can be switched between high and low speed. When the oscillation source (fosc) is 8 MHz, a machine cycle lasts for 250 ns. When fosc is 20 MHz, a machine cycle is 100 ns. The package are available with three types of 42-pin SDIP, 44-pin QFP and 48-pin QFH.
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1-1-2 Product Summary
This manual describes the following models of the MN101C11 series. These products have identical functions. Table 1-1-1 Product Summary
Model MN101C115*1 MN101C117 MN101CP117 1 Under development
ROM Size 8 KB 16 KB 16 KB
RAM Size 256 bytes 512 bytes 512 bytes
Classification Mask ROM version Mask ROM version EPROM version
2
Product Overview
Chapter 1 Overview
1-2 Hardware Functions
ROM/RAM Size: Internal ROM2 16,384x8-bit*3 Internal RAM2 Machine Cycles: 512x8-bit
2 Differs depending upon the model. [ 1-1-2 "Product Summary"] *3 Bit 8 of the last address for the built-in ROM of MN101C11X is an optional bit; therefore, this cannot be used as an ordinary ROM. *4 Exclusive for a 48-pin QFH product.
High speed mode 0.10s/20MHz (4.5V to 5.5V) 0.25s/8MHz(2.7V to 5.5V) 1.00s/2MHz(2.0V to 5.5V) Low speed mode 125s/32KHz(2.0V to 5.5V)*4 12 interrupts(11 interrupts except for 48-pin QFH package) The active edge can be selected for all external interrupts IRQ0 External interrupt (can be connected to noise filter) IRQ1 External interrupt (can determine zero crossings, can be connected to noise filter) IRQ2 External interrupt IRQ3 External interrupt *4 TM2IRQ Timer 2 (8-bit timer) TM3IRQ Timer 3 (8-bit timer) TM4IRQ Timer 4 (16-bit timer) TM5IRQ Timer 5 (8-bit timer) TBIRQ Clock timer interrupts SC0IRQ Serial 0 (synchronous + simple UART ADIRQ A/D conversion complete NMI Overflow of watchdog timer
Interrupts:
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Timer/Counters:five timers, all can generate interrupts Timer 2 8-bit timer
Square wave output, 8-bit PWM output are possible, Clock source: fs, fs/4, fx*4, TM2IO pin input Timer 3 8-bit timer
Square wave output, synchronous serial/UART baud rate timer Clock source: fosc, fs/4, fs/16, TM3IO pin input Remote control carrier can be generated.
Hardware Functions
3
Chapter 1 Overview
Timers 2 and 3 can be cascaded. Timer 4 16-bit timer
Square wave output, 16-bit PWM output are possible. Clock source: fosc, fs/4, fs/16, TM4IO pin input Input capture function Time base timer Clock source: fosc, fs/4, fx*4, fx/213*4 or fosc/213 XIOat 32kHz, can be set to measure one minute intervals*4 Can operate independently as timer 5 (8-bit timer). Watchdog timer Selected by the mask option as fs/216, fs/218, or fs/220 Remote control carrier output: Buzzer output: Serial interface: Based on the timer output, a remote control carrier with duty ratio of 1/2, 1/3 can be output. Output frequency can be selected from fs/29, fs/210, fs/211 or fs/212. Synchronous/ Simple UART (half-duplex) Transfer clock: fs/2, fs/4, fs/16, 1/2 of timer 3 output When using timer 3, the transfer rates for a 12MHz oscillation are 19200/9600/4800/2400/1200/300 bps. MSB or LSB can be selected as the first bit for transfer. An arbitrary transfer size of 1 to 8 bits can be selected. 10 bits x 8 channels
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A/D converter:
LED driver function:8 pins Ports:
5
26 ports for 44-QFP 27 ports for 48-QFH
6 7
12 ports for 48-QFH 4 ports for 48-QFH
I/O ports 25 ports (8 have dual functions)*5 LED (large current) driver ports: 8 ports (push-pull configuration) Input ports 11 ports (all have dual functions) *6 Number of pins with dual function for external interrupts: 3*7 (One of which can also be used for zero-cross input.) Number of pins with dual function for A/D input: 8 Operation mode input pin: 1 Reset input pin: 1
Operation modes: NORMAL mode SLOW mode*4 HALT mode STOP mode and switches operating clock*4 Package: 42-SDIP, 44-QFP, 48-QFH
4
Hardware Functions
Chapter 1 Overview
1-3 Pins
1-3-1 Pin Diagram
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Figure 1-3-1 Pin Diagram (42-SDIP: TOP VIEW)
Pins
5
Chapter 1 Overview
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Figure 1-3-2 Pin Diagram (44-QFP: TOP VIEW)
6
Pins
Chapter 1 Overview
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Figure 1-3-3 Pin Diagram (48-QFH: TOP VIEW)
Pins
7
Chapter 1 Overview
1-3-2 Pin Function Summary
*The pin numbers in the list correspond to the QFH package(Refer to Figure 1-3-3 Pin connection.) Be careful when using SDIP and QFP packages. Table 1-3-1 Pin Function Summary (1/4)
Pin No. 17 14 16 15 Name VSS VDD OSC1 OSC2 Type - Input Output Dual Function Function Power supply pins Clock input pin Clock output pin Description Apply 2.0V to 5.5V to VDD and 0V to VSS. Connect these oscillation pins to ceramic or crystal oscillators for highspeed clock operation. If the clock is an external input, connect it to OSC1 and leave OSC2 open. The chip will not operate with an external clock when using either the STOP or SLOW modes. Connect these oscillation pins to ceramic or crystal oscillators for lowspeed clock operation. If the clock is an external input, connect it to XI and leave XO open. The chip will not operate with an external clock when using the STOP mode. If these pins are not used, connect XI to VSS and leave XO open. *42-SDIP and 44-QFP packages have no pins of this kind. This pin resets the chip when power is turned on, is allocated as P27 and contains an internal pull-up resistor (Typ. 35 k). Setting this pin low initializes, the internal state of the device is initialized. Thereafter, setting the input to an"H"level release the reset The hardware waits for the system clock to stabilize, and then processes the reset interrupt. Also, if "0" is written to P27 and the reset is initiated by software, a low level will be output. The output has an n-channel open-drain configuration. If a capacitor is to be inserted between RST and VDD, it is recommended that a discharge diode be placed between RST and VDD. 4-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P0DIR register. A pull-up resistor for each bit can be selected individually by the P0PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output).
18 19
XI XO
Input Output
Clock input pin Clock output pin
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43
RST
I/O
P27
Reset pin
20 to 23
P00 to P02 I/O P06
SBO0(TXD), I/O port 0 SBI0(RXD), SBT0, DK (BUZZER)
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Pins
Chapter 1 Overview
Table 1-3-1 Pin Function Summary (2/4)
Pin No. 24 to 28
Name P10 to P14
Type I/O
Dual Function RMOUT, TM2IO to TM4IO
Function I/O port 1
Description 5-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by theP1DIR register. A pull-up resistor for each bit can be selected individually by the P1PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). 4-bit input port. A pull-up resistor for each bit can be selected individually by the P2PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). P23 pin does not exist for 42-SDIP, 44-QFP packages. Port P27 has an n-channel open-drain configuration. When "0" is written and the reset is initiated by software, a low level will be output. 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P6DIR register. A pull-up resistor for each bit can be selected individually by the P6PLU register. At reset, the input mode is selected and pull-up resistors for P60 to P67 are disabled (high impedance output).
29 to 32
P20 to P23
Input
IRQ0, Input port 2 IRQ1(SENS), IRQ2 to 3 RST Input port 2
43
P27
Input
33 to 40
P60 to P67
I/O
I/O port 6
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41 to 42
P70 to P71 I/O
I/O port 7
2-bit CMOS tri-state I/O port. Each individual bit can be switched to an input or output by the P7DIR register. A pull-up or pull-down resistor for each bit can be selected individually by the P7PLUD register. However, pull-up and pull-down resistors cannot be mixed. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). P70 and P71 pins do not exist for 42-SDIP package. P71 pin does not exist for 44-QFP package, either. 8-bit CMOS tri-state I/O port. Each individual bit can be switched to an input or output by the P8DIR register. A pull-up resistor for each bit can be selected individually by the P8PLU register. When configured as outputs, these pins can drive LED segments, directly. At reset, the input mode is selected and pull-up resistors for P80 to P87 are disabled (high impedance output). 8-bit input port. A pull-up or pull-down resistor for each bit can be selected individually by the PAPLUD register. However, pull-up and pulldown resistors cannot be mixed. At reset, the PA0 to PA7 input mode is selected and pull-up resistors are disabled.
1 to 4 45 to 48
P80 to P87 I/O
LED0 to 7
I/O port 8
6 to 13
PA0 to PA7 Input
AN0 to AN7
Input port A
Pins
9
Chapter 1 Overview
Table 1-3-1 Pin Function Summary (3/4)
Pin No. 20 21 Name TXD RXD Type Output Input Dual Function SBO0(P00) SBI0(P01) Function UART transmit data output pin UART receive data input pin Description In the serial interface in UART mode, these pins are configured as the receive data input pin and transmit data output pin. A push-pull or n-channel open-drain configuration can be selected for TXD by the SC0MD1 register. Pull-up resistors can be selected by the P0PLU register. The TXD and RXD pins are also allocated as P00 and P01 respectively. When not used as serial/UART pins, these can be used as normal I/O pins. Transmit data output pin for serial interfaces 0. The output configuration, either CMOS push-pull or n-channel open-drain, and pull-up resistors can be selected by the software. Set these pins to the output mode by the P0DIR register. SBO0 is allocated as P00. This may be used as normal I/O pin when the serial interface is not used. Receive data input pin for serial interfaces 0. Pull-up resistor can be selected by the P0PLU register. Set these pins to the input mode by the P0DIR register. SBI0 is allocated as P01. This can be used as normal I/O pin when the serial interface is not used. Clock I/O pin for serial interface 0. The output configuration, either CMOS push-pull or n-channel open-drain output, can be selected by the software. The direction of SBT0 is selected by the P0DIR register in accordance with the communication mode. Pull-up resistors can be selected by the P0PLU register. SBT0 is allocated as P02. This can be used as normal I/O pin when the serial interface is not used. Piezoelectric buzzer driver pin. The driving frequency can be selected in the range of fs/2 to fs/2 by the DLYCTR register. Select output mode by the P0DIR register and select buzzer output by the DLYCTR register. When not used for buzzer output, this pin can be used as a normal I/O pin. Output pin for remote control transmit signal with a carrier signal. Can be used as a normal I/O pin when remote control is not used. Event counter clock input pins, overflow pulse output pins and PWM signal output pins for timer 2 to 4. To use these pins as event clock inputs, configure them as inputs by the P1DIR register. For overflow pulse and PWM output, configure these pins as outputs by the P1DIR register. When the pins are used as inputs, pull-up resistors can be specified by the P1PLU register. When not used for timer I/O, these can be used as normal I/O pins.
20
SBO0
Output
TXD(P00)
Serial interface transmit data output pin
21
SBI0
Input
RXD(P01)
Serial interface receive data input pin
22
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SBT0
I/O
P02
Serial interface clock I/O pin
22
Buzzer
I/O
P06
Buzzer output
24
RMOUT
I/O
P10
Remote control transmit signal output pin Timer I/O pins
26 to 28
TM2IO to TM4IO
I/O
P12 to P14
10
Pins
Chapter 1 Overview
Table 1-3-1 Pin Function Summary (4/4)
Pin No. 44 Name MMOD Type Input Dual Function Function Test mode switch input pin P20, P21(SENS), P22,P23 External interrupt input pins This pin sets the test mode. Must be set to L. The valid edge for these external interrupt input pins can be selected with the IRQnICR registers. IRQ1 is an external interrupt pin that is able to determine AC zero crossings. It can also be used as a normal external interrupt. When IRQ0 to 3 are not used for interrupts, these can be used as normal I/O pins. Description
29 to 32
IRQ0 to IRQ3
Input
6 to 13
AN0 to AN7 Input
PA0 to PA7
Analog input pins Analog input pins for an 8-channel, 10-bit A/D converter. When not used for analog input, these pins can be used as normal I/O pins. SENS is an input pin for an AC zero-cross detection circuit. The AC zeroAC zero-cross detection input pin cross circuit outputs a high level when the input is at an intermediate level. It outputs a low level at all other times. SENS is connected to the P21 input circuit and the IRQ1 interrupt circuit. When the AC zero-cross detection circuit is not used, this pin can be used as a normal P21 input. The P21IM flag of the FLOAT1 register sets which input is selected.
30
SENS
Input
IRQ1(P21)
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Pins
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Chapter 1 Overview
1-4 Overview of Functions
1-4-1 Block Diagram
OSC1
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TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 P06 RMOUT,P10 P11 TM2IO,P12 TM3IO,P13 TM4IO,P14 IRQ0,P20 SENS,IRQ1,P21 IRQ2,P22 IRQ3,P23 RST,P27 AN7,PA7 AN6,PA6 AN5,PA5 AN4,PA4 AN3,PA3 AN2,PA2 AN1,PA1 AN0,PA0
Port 0
XO
RST MMOD
OSC2
VSS VDD
XI
Sub-clock oscillator Port 1 ROM 16 KB
RAM 512 bytes External interrupt Serial interface 0 Time base timer 5 Watchdog timer
Port 2
8-bit timer 2 8-bit timer 3 16-bit timer 4
Port 7
Port 6
System clock oscillator
CPU MN101C00
P60 P61 P62 P63 P64 P65 P66 P67 P70 P71
Figure 1-4-1 Block Diagram of Functions)
12
Overview of Function
Port 8
A/D conversion
P80,LED0 P81,LED1 P82,LED2 P83,LED3 P84,LED4 P85,LED6 P86,LED6 P87,LED7
Port A
Chapter 1 Overview
1-5 Electrical Characteristics
Contents Model MN101C117/115 CMOS integrated circuit General purpose CMOS, 8-bit, single-chip microcomputer Classification Use Function
This LSI manual describes standard specifications. Before using the LSI, please obtain product specifications from the sales office.
1-5-1 Absolute Maximum Ratings
Parameter 1 2 3
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2 3
Symbol VDD IC VI VO VIO1 P8 I OL1 (peak) I OL2 (peak) I OH (peak) I OL1 (avg)
Rating -0.3 to +7.0 -500 to 500 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 30 20 -10
Unit V A V V V
Supply voltage Input clamp current (SENS) Input pin voltage Output pin voltage I/O pin voltage
4 5 6 7 8 9 10 11 12 13 14
Peak output current
Except P8 All pins P8
mA 20 15 -5 400 -40 to 85 -55 to +125 mW C C
Average output Other than P8 I OL2 (avg) current*1 All pins Tolerable loss Ambient operating temperature Storage temperature
1 *2
I OH (avg) PD Topr Tstg
Note:
Applicable even for an interval of 100ms. Insert at least one bypass capacitor of 0.1F or more between a power source pin and GND to prevent from latchup. *3 Absolute maximum ratings indicate the allowable limit to which applied voltage does not damage a chip, not guarantee the operation.
Electrical Characteristics
13
Chapter 1 Overview
1-5-2 Operating Conditions
Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions MIN Rating TYP MAX Unit
Supply voltage
1 2 Supply voltage 3 during operation VDD1 VDD2 VDD3 VDD4 Voltage to maintain RAM data VDD5
2
fosc 20.0MHz fosc 8.39MHz fosc 2.00MHz
4.5 2.7 2.0 2.0 1.8
5.5 5.5 V 5.5 5.5 5.5
4 5
*1
fx = 32.768kHz STOP mode
Operating speed
6 7
tc1 tc2 Instruction execution time tc3 tc4 *
1
VDD=4.5 to 5.5V VDD=2.7 to 5.5V VDD=2.0 to 5.5V VDD=2.0 to 5.5V
0.100 0.238 1.00 40 125 s
8 9
Crystal oscillator 1 Fig. 1-5-1
10 Crystal frequency
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fxtal 1 C11 C12
VDD=4.5 to 5.5V
1.0 20
20.0
MHz pF
11 External capacitors 12
20 700
1
13 Internal feedback resistor RF10
k
Crystal oscillator 2 Fig. 1-5-2*
14 Crystal frequency 15 External capacitors 16
fxtal 2 C21 C22
32.768 20 20 4.0
kHz pF M
17 Internal feedback resistor RF20
Note:
*1. Only for 48-QFH package 2 t c1, t c2, t c3: OSC1 is the CPU clock t c4: XI is the CPU clock
XI 4.0M Typ MN101C C12 C11 fxtal2
OSC1 700k Typ MN101C fxtal1
OSC2
XO C22 C21
The instruction cycle is twice the clock cycle. The feedback resistor is built-in. Figure 1-5-1 Crystal Oscillator 1
The instruction cycle is four times the clock cycle. The feedback resistor is built-in. Figure 1-5-2 Crystal Oscillator 2 *1
14
Electrical Characteristics
Chapter 1 Overview
Parameter
Symbol
Conditions MIN
Rating TYP MAX
Unit
External clock input 1 OSC1 (OSC2 is unconnected)
18 Clock frequency 19 High level pulse width 20 Low level pulse width 21 Rise time 22 Fall time
fOSC twh 1
1
1.0 20.0 Fig. 1-5-3 20.0 Fig. 1-5-3
20.0 30.0
MHz ns
twl 1 twr 1 twf 1
30.0 5.0 ns 5.0
External clock input 2 XI (XO is unconnected)*2
23 Clock frequency 24 High level pulse width
fx twh 2
1
32.768 3.5 Fig. 1-5-4 3.5
100
kHz s
25 Low level pulse width 26 Rise time 27 Fall time
twl 2 twr 2 Fig. 1-5-4 twf 2
20 ns 20
1 Set the clock duty ratio to 45 to 55%. *2 Applicable only for 48-pin QFH package
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Electrical Characteristics
15
Chapter 1 Overview
0.9VDD
0.1VDD
twh1 twr1 twf1
twl1
Figure 1-5-3 OSC1 Timing Chart
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0.9VDD
0.1VDD
twh2 twr2 twf2
twl2
Figure 1-5-4 XI Timing Chart
16
Electrical Characteristics
Chapter 1 Overview
1-5-3 DC Characteristics
Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol
1
Conditions MIN
Rating TYP MAX
Unit
Supply current (no load at output)
1 Supply current 2 during operation 3 IDD1 IDD2 IDD3
*2
fosc=20.0MHz,VDD=5V fosc=8.39MHz,VDD=5V fx =32.768kHz,VDD=3V fx =32.768kHz,VDD=3V Ta=25 Ta=-40 to 85C VDD=5V, Ta=25C VDD=5V, Ta=-40 to 85C
gY0@@@4I? f?Y.Oe?K)4V? fY.W?fX)'V f5Jg?L@3 f@? gh1@N? ghL@3? h?@@? gh?@@? gh?@@? gh?@@? gh?@@? gh?@@? ghH@7? gh5@ f'Vg?H@7J?Y0@4V? f1'I?fY(&We fL@@4I??M(2W?e5C?=@? 3? f?@2T6@@2O?f@?e7? 1B?< X6@2W?
25 10
60 mA 25 100 8
4
Supply current during HALT mode
IDD5 *2 IDD6*2
5 6
Supply current during STOP mode
18 0 0 2 20
A
IDD7 IDD8
7
Notes:
1
Measured under conditions of Ta=25C and no load. The supply current during operation, I DD1 (I DD2 ), is measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to , the MMOD pin is fixed at VSS, the input pins are fixed at VDD, and a 20MHz (8.39MHz) square wave of amplitude VDD,VSS is input to the OSC1 pin. The supply current during operation, IDD3, is measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to , the MMOD pin is fixed at VSS, the input pins are fixed at VDD, and a 32.768kHz square wave of amplitude VDD,VSS is input to the XI pin. The supply current during HALT mode, IDD5(IDD6), is measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to , the MMOD pin is fixed at VSS, the input pins are fixed at VDD, and an 32.768kHz square wave of amplitude VDD,VSS is input to the XI pin. The supply current during STOP mode IDD7(IDD8) is measured under the following conditions: After the oscillation mode is set to , the MMOD pin is fixed at VSS, the input pins are fixed at VDD, and the OSC1 and XI pins are
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*2
unconnected. The items IDD5(IDD6) and IDD7(IDD8) are applicable only for 48-pin QFH package.
Electrical Characteristics
17
Chapter 1 Overview
Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions MIN Rating TYP MAX Unit
Input pin 1 MMOD
8 9 Input high voltage 1 Input high voltage 2 VIH1 VIH2 VIL1 VIL2 ILK1 VDD=4.5 to 5.5V VIN = 0 to VDD VDD=4.5 to 5.5V 0.8VDD 0.7VDD 0 0 VDD VDD 0.2VDD 0.3VDD 10 V V V V A
10 Input low voltage 1 11 Input low voltage 2 12 Input leakage current
Input pin 2 P20, P22~P23 (Schmitt trigger input)
13 Input high voltage 14 Input low voltage 15 Input leakage current 16 Input high current VIH3 VIL3 ILK3 IIH3 VIN=0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor ON
0.8VDD 0
VDD 0.2VDD 10
V V A A
-30
-100
-300
Input pin 3--1 P21 (Schmitt trigger input)
17 Input high voltage 18 Input low voltage 19 Input leakage current
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VIH4 VIL4 ILK4 IIH4 VIN=0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor ON
0.8VDD 0
VDD 0.2VDD 10
V V A A
20 Input high current
-30
-100
-300
Input pin 3--2 P21 (when used as SENS)
21 Input high voltage 1 22 Input low voltage 1 23 Input high voltage 2 24 Input low voltage 2 25 Input leakage current 26 Input clamp current VDHH VDLH VDHL VDLL ILK10 IC10 VIN=0V to VDD
VDD=5.0V VIN>VDD, VIN<0V
VDD=5.0V Fig. 1-5-5
4.5 VSS 1.5 VSS
VDD 3.5 VDD 0.5 10
V
V
A 400
18
Electrical Characteristics
Chapter 1 Overview
SENS pin
27 28
Rise time Fall time
trs
Fig. 1-5-5
30 30
trs tfs
tfs
s
Input voltage level 1
VDD VDHH VDLH (Input)
Input voltage level 2
VDHL VDLL VSS
(Output)
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Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit
Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions MIN Rating TYP MAX Unit
Input pin 4 PA0~PA7
29 Input high voltage 1 30 Input high voltage 2 31 Input low voltage 1 32 Input low voltage 2 33 Input leakage current 34 Input high current 35 Input low current VIH5 VIH6 VIL5 VIL6 ILK5 IIH5 IIL5 VDD=4.5 to 5.5V VIN=0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor ON VDD=5V, VIN=3.5V Pull-down resistor ON
0.8VDD VDD=4.5 to 5.5V 0.7VDD 0 0
VDD VDD 0.2VDD 0.3VDD 2
V V V V A A A
-30 80
-100 180
-300 400
Electrical Characteristics
19
Chapter 1 Overview
Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions MIN Rating TYP MAX Unit
I/O pin 5 P27 (RST)
36 Input high voltage 37 Input low voltage 38 Input leakage current 39 Input high current VIH7 VIL7 ILK7 Iih VIN = 0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor built in
0.9VDD 0
VDD 0.2VDD 10
V V A A
-30
-100
-300
I/O pin 6 P00 to P06, P10 to P14 (Schmitt trigger input)
40 Input high voltage 41 Input low voltage 42 Input leakage current 43 Input high current 44 Output high voltage 45 Output low voltage VIH8 VIL8 ILK8 IIH8 VOH8 VOL8 VIN=0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor ON
0.8VDD 0
VDD 0.2VDD 10
V V A A V
-30 4.5
-100
-300
VDD = 5V, IOH = -0.5mA VDD = 5V, IOL = 1.0mA
0.5
V
I/O pin 7 , P60 to P67
46 Input high voltage 1 47 Input high voltage 2 48 Input low voltage 1
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VIH9 VIH10 VIL9 VIL10 ILK9 IIH9 VOH9 VOL9 VDD=4.5 to 5.5V VIN=0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor ON
0.8VDD VDD=4.5 to 5.5V 0.7VDD 0 0
VDD VDD 0.2VDD 0.3VDD 10
V V V V A A V
49 Input low voltage 2 50 Input leakage current 51 Input high current 52 Output high voltage 53 Output low voltage
-30 4.5
-100
-300
VDD = 5V, IOH = -0.5mA VDD = 5V, IOL = 1.0mA
0.5
V
I/O pin 8 P70 to P71
54 Input high voltage 1 55 Input high voltage 2 56 Input low voltage 1 57 Input low voltage 2 58 Input leakage current 59 Input high current 60 Input low current 61 Output high voltage 62 Output low voltage VIH11 VIH12 VIL11 VIL12 ILK11 IIH11 IIL11 VOH11 VOL11 VDD=4.5 to 5.5V VIN = 0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor ON VDD=5V, VIN=3.5V Pull-down resistor ON
0.8VDD VDD=4.5 to 5.5V 0.7VDD 0 0
VDD VDD 0.2VDD 0.3VDD 10
V V V V A A A V
-30 30 4.5
-100 100
-300 300
VDD = 5V, IOH = -0.5mA VDD = 5V, IOL = 1.0mA
0.5
V
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Electrical Characteristics
Chapter 1 Overview
Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions MIN Rating TYP MAX Unit
I/O pin 9 P80~P87
63 Input high voltage 1 64 Input high voltage 2 65 Input low voltage 1 66 Input low voltage 2 67 Input leakage current 68 Input high current 69 Output high voltage 70 Output low voltage VIH13 VIH14 VIL113 VIL14 ILK13 IIH13 VOH13 VOL13 VDD=4.5 to 5.5V VIN=0 to VDD
VDD=5V, VIN=1.5V Pull-up resistor ON
0.8VDD VDD=4.5 to 5.5V 0.7VDD 0 0
VDD VDD 0.2VDD 0.3VDD 10
V V V V A A V
-30 4.5
-100
-300
VDD = 5V, IOH = -0.5mA VDD = 5V, IOL = 15mA
1.0
V
1-5-4 A/D Converter Characteristics
Ta=-40 to+85C VDD=2.0 to 5.5V VSS=0V
Rating Parameter
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Symbol
Conditions MIN TYP MAX 10 VDD = 5.0V, VSS = 0V VREF+=5.0V, VREF-=0V TAD = 800ns VDD = 5.0V, VSS = 0V VREF-=5.0V, VREF-=0V fx = 32.768kHz VDD = 5.0V, VSS = 0V VREF+=5.0V, VREF-=0V TAD = 800ns TAD = 800ns 9.6 183 1.0 30.5 2 36 30 30 3 3 5 5 100 100
Unit Bits LSB LSB LSB LSB mV mV s s s s A
1 2 3 4 5 6 7 8 9 10 11
Resolution Nonlinear error 1 Differential linear error 1 Nonlinear error 2 Differential linear error 2 Zero traction voltage Full-scale transition voltage
A/D conversion time
fx = 32.768kHz fOSC = 8MHz
Sampling time
fx = 32.768kHz When VDAIN = 0 to 5V is off
12 Analog input leakage current
Electrical Characteristics
21
Chapter 1 Overview
1-6 Option
1-6-1 ROM Option
The product equipped with this LSI or an EPROM with this LSI controls the oscillation mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to 0 of the last address of the built-in ROM. s Option bits
7
6
5
4 PKG SEL2
3
2
1
0
PKG WDSEL2 WDSEL1 NSSTRT SEL1
NSSTRT 0 1
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Selection of oscillation mode after resetting SLOW mode NORMAL mode
WDSEL2 WDSEL1 Watchdog timer cycle setting 0 1 0 1
fs/2 16 fs/2 18 fs/2 20
PKGSEL2 PKGSEL1 0 1 0 1
Packages SDIP042-P-0600 QFP044-P-1010 QFH048-P-0707
Figure 1-6 ROM Option ( Address:X'7FFF' )
22
Option
Chapter 1 Overview
1-6-2 Option Form
Date: SE No.
Model Name
MN101C
Customer
Approval
1. Oscillation mode Type A Type B
Note: Type A: Operation begins from the reset cycle in the NORMAL mode. Type B: Operation begins from the reset cycle in the SLOW mode.
2. Watchdog timer period setting Detection Period fs/2
16
3. Package selection Package SDIP042-P-0600 QFP044-P-1010 QFH048-P-0707 Selection
Selection
fs/218
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fs/2
20
Not used
Contents of mask option are subject to change. When placing an order for masks, please request the most recent option list from the sales office.
Option of this product is used a part of the built-in ROM. When placing an order for programme, please sed data on the address of the option.
Chapter 1 Overview
23
Chapter 1 Overview
1-7 Outline Drawings
Package code: SDIP042-P-0600 Unit: mm
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Body Material: Epoxy Resin
Lead Material:Fe Ni
Lead Finish Method:Soldering dip
Figure 1-7-1 42-SDIP
The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
24
External Dimensions
Chapter 1 Overview
Package code: QFP044-P-1010 Unit: mm
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Body Material: Epoxy Resin
Lead Material:Fe Ni
Lead Finish Method:Soldering dip
Figure 1-7-2 44-QFP
The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
External Dimensions)
25
Chapter 1 Overview
Package code: QFH048-P-0707 Unit: mm
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Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy Lead Finish Method:Soldering dip
Figure 1-7-3 48-QFH
The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
26
External Dimensions
Chapter 2
Basic CPU Functions
2
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27
Chapter 2 Basic CPU Functions
2-1 Overview
Basic CPU functions are in conformance with the MN101C00 series manual (architecture manual). This chapter describes specifications unique to the MN101C117/115.
2-2 Address Space
2-2-1 Memory Configuration
X'00000' 256 bytes 512 bytes
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Abs 8 addressing access area X'00100' Data X'00200' X'03F00'
Internal RAM space
256 bytes X'04000' 128 bytes X'04080' 64 bytes 16 KB X'040C0'
Special function registers Interrupt vector table Subroutine vector table
Internal ROM space
Instruction code/ table data X'07FFF'
Figure 2-2-1 Memory Map Differs depending upon the model. MN101C115 Internal RAM X'00000' to X'000FF' Internal ROM X'04000' to X'05FFF' MN101CP117 Internal RAM X'00000' to X'001FF' EP ROM X'04000' to X'01FFF'
256 bytes 8 KB 512 bytes 16 KB
28
Overview/Address Space
Chapter 2 Basic CPU Functions
2-2-2 Special Function Registers
Memory control register(MEMCTR) is a 4-bit register which set up the base
Table 2-2-1 Register Map
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CPU mode, memory control
03F0X CPUM MEMCTR WDCTR DLYCTR 03F1X P0OUT P1OUT P2OUT 03F2X P0IN P1IN P2IN 03F3X P0DIR P1DIR 03F4X P0PLU P1PLU P2PLU
P6OUT P7OUT P8OUT P6IN P7IN P8IN PAIN
Port output Port input I/O mode control Resistor control
P6DIR P7DIR P8DIR P1OMD PAIMD P6PLU P7PLUD P8PLU PAPLUD FLOAT1
03F5X SC0MD0 SC0MD1 SC0MD2 SC0MD3 SC0CTR SC0TRB SC0RXB 03F6X 03F7X
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Serial interface control
TM2BC TM3BC TM4BCL TM4BCH TM4ICL TM4ICH TM5BC TM2OC TM3OC TM4OCL TM4OCH TM2MD TM3MD TM4MD TM5OC TM5MD RMCTR NFCTR
Timer control
03F8X
03F9X ANCTR0 ANCTR1 ANBUF0 ANBUF1 03FAX 03FBX
A/D control
Reserved 03FCX 03FDX 03FEX 03FFX TM5ICR
NMICR IRQ0ICR IRQ1ICR TM2ICR TBICR SC0ICR ADICR IRQ2ICR TM3ICR TM4ICR
Interrupt control
I/O ports
Address Space
29
Chapter 2 Basic CPU Functions
2-3 Bus Interface
2-3-1 Overview
The MN101C117, unlike other MN101C series microcomputers, does not support memory expansion mode and processor mode.
2-3-2 Control Registers
The memory control register is a four-bit register that sets up wait-count at a time of access to a base address of interrupt vector table and a special register zone. (1) Memory control register(MEMCTR)
7 MEMCTR 6 5 4 3 2 IRWE 1 0
IOW1 IOW0 IVBA
(at reset: 11001011)
Must be set to 11.
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IRWE
Set software write for interrupt request flag Software write disable Even if data is written to each interrupt control register (xxxICR), the state of the interrupt request flag (xxxIR) will not change. Software write enable
0 1
Must be set to 1.
Must be set to 0
IVBA 0 1
Base address setting for interrupt vector table Interrupt vector base = X'04000' Interrupt vector base = X'00100'
IOW1 to 0 00 01 10 11
Bus cycle at Number of wait cycles set when accessing special register area 20MHz oscillation No wait cycles 1 wait cycle 2 wait cycles 3 wait cycles 100ns 150ns 200ns 250ns
Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/W
30
Bus Interface
Chapter 2 Basic CPU Functions
2-4 Interrupts
2-4-1 Accepting and Returning from Interrupts
In the MN101C00 series, when an interrupt is accepted, the hardware pushes the program's return address and the PSW, on to the stack, and branches to the beginning address of the interrupt program specified by the interrupt vector table. s Operation when Interrupt is Accepted 1. 2. The stack pointer (SP) contents are update. (SP-6 SP) The handy address register (HA) is pushed on to the stack. HA upper byte (SP+5) HA lower byte (SP+4) The program counter (PC = return address) contents are pushed on to the stack. PC (bit 18 to bit 17, bit 0) (SP+3) PC (bit 16 to bit 9) (SP+2) PC (bit 8 to bit 1) (SP+1) The PSW is pushed on to the stack. PSW (SP) xxxLVn of the accepted interrupt is copied to IM of the PSW. Interrupt level IM Execution branches to vector table.
7 0 7 0 PSW PSW PC8 to 1 PC8 to PC16 to 91 PC0 PC0 PC16 to 9PC18,17 HA7 to 0 HA7 to HA15 to 80 PC18,17
3.
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4. 5. 6.
New SP (after interrupt is accepted) New SP (after interrupt is accepted)
Low Low Address Address High High
Old SP (before interrupt SPaccepted) Old is (before interrupt is accepted)
HA15 to 8
Figure 2-4-1 Stack Status during an Interrupt
Since the contents of data and address registers are not saved, use PUSH instructions in the program to save these values as necessary on the stack.
Interrupts
31
Chapter 2 Basic CPU Functions
s Operation when Returning from Interrupt After the program POPs the register and other values saved by the interrupt service routine, an RTI instruction is implemented to return to the program that was being executed when the interrupt was received. The processing sequence for the return from interrupt instruction, RTI, is listed below. 1. 2. 3. 4. 5. The processor status word (PSW) is pulled from the stack. (SP) The program counter(PC = return address) is pulled from the stack. (SP+1 to 3) The handy address register (HA) is pulled from the stack. (SP+4, 5) The SP is pulled. (SP+6 SP) Execution branches to the address indicated by the PC.
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32
Interrupts
Chapter 2 Basic CPU Functions
2-4-2 Interrupt Sources and Vector Addresses
In addition to reset, there are 20 interrupt vectors that indicate the starting addresses of interrupt programs. These vectors are located in the 80-byte ROM address area X'04004' to X'04053'.
Table 2-4-1 Interrupt Control Registers
Vector Number 0 1 2 3 4 5 6 7
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Interrupt Source Reset Non-maskable interrupt (NMI) External interrupt 0 (IRQ0) External interrupt 1 (IRQ1) Reserved Reserved Timer 2 compare-match (TM2IRQ) Time base period (TBIRQ) SC0 transfer complete (SC0IRQ) Reserved
Control Register (address)
Vector Address X'04000'
NMICR
(X'03FE1')
X'04004' X'04008' X'0400C' X'04010' X'04014' X'04018' X'0401C' X'04020' X'04024' X'04028' X'0402C' X'04030' X'04034' X'04038' X'0403C' X'04040' X'04044' X'04048' X'0404C' X'04050'
IRQ0ICR (X'03FE2') IRQ1ICR (X'03FE3') (X'03FE4') (X'03FE5') TM2ICR TBICR SC0ICR (X'03FE6') (X'03FE7') (X'03FE8') (X'03FE9') (X'03FEA')
8 9 10 11 12 13 14 15 16 17 18 19 20
A/D conversion complete (ADIRQ) ADICR External interrupt 2 (IRQ2) External interrupt 3 (IRQ3)* Reserved Timer 3 compare-match (TM3IRQ) Timer 4 compare-match (TM4IRQ) Timer 5 compare-match (TM5IRQ) Reserved Reserved Reserved Reserved TM3ICR TM4ICR
IRQ2ICR (X'03FEB') IRQ3ICR (X'03FEC') (X'03FED') (X'03FEE') (X'03FEF')
*IRQ31CR cannot be used
except for 48-pin QFH package.
TM5ICR (X'03FF0') (X'03FF1') (X'03FF2') (X'03FF3') (X'03FF4')
Set the vector addresses for reserved and unused interrupts to an address containing an RTI instruction.
Interrupts
33
Chapter 2 Basic CPU Functions
2-4-3 Interrupt Control Registers
Interrupt control registers consist of the following: a non-maskable interrupt control register (NMICR), external interrupt control registers (IRQnICR), and internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR).
Be sure to use the MIE flag of the PSW register to write to all interrupt control registers.
s Non-maskable Interrupt Control Register (NMICR) Non-maskable interrupt factors are stored in the non-maskable interrupt control register (NMICR), and are used when a non-maskable interrupt is generated.
7 NMICR 6 5 4 3 2 1 WDIR 0 (at reset: ------0-)
WDIR 0 1
Watchdog interrupt request flag No interrupt request Happens interrupt request
Figure 2-4-2 Non-maskable Interrupt Control Register (NMICR: X'03FE1', R/W) s External Interrupt Control Registers (IRQnICR) The external interrupt control registers (IRQnICR) control the interrupt level, valid edge, and request/enable.
7 6 5 4 -- 3 -- 2 -- 1 0 (at reset: 000---00)
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By setting xxxLVn to '11' (level 3), the corresponding interrupt vector will be disabled, regardless of the state of the interrupt enable and interrupt request flags.
IRQnICR
xxxLV1 xxxLV0 REDGn
xxxIE xxxIR
xxxIR 0 1
External interrupt request flag No interrupt request Happens interrupt request
xxxIE 0 1
External interrupt enable flag Disable interrupt Enable interrupt
REDGn 0 1
External interrupt valid edge flag Falling edge Rising edge
xxxLV1 xxxLV0 Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3. This flag sets the interrupt level for interrupt requests.
n=0,1,2,3,4
Figure 2-4-3 External Interrupt Control Register (IRQnICR: X'03FE2' to X'03FE3', X'03FEB' to X'03FED', R/W)
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Interrupts
Chapter 2 Basic CPU Functions
s Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR) The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial interrupts, A/D conversion complete interrupts, and interrupt request/enable. Be sure to disable all interrupts before writing to these registors.
7 6 5 - 4 - 3 - 2 - 1 0 (at reset: 00----00)
TMnICR, TBICR, SCnICR, xxxLV1 xxxLV0 ATCICR, ADICR
xxxIE xxxIR
By setting xxxLVn to '11' (level 3), the corresponding interrupt vector will be disabled, regardless of the state of the interrupt enable and interrupt request flags.
xxxIR 0 1
Interrupt request flag No interrupt request Happens interrupt request
xxxIE 0 1
Interrupt enable flag Disable interrupt Enable interrupt
xxxLV1 xxxLV0
Interrupt level flag
This 2-bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests.
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Figure 2-4-4 Internal Interrupt Control Registers (TMnICR, TBICR, SC0ICR,ADICR: X'03FE6' to X'03FEA', X'03FEA' to X'03FF0', R/W)
Interrupts
35
Chapter 2 Basic CPU Functions
2-5 Reset
The CPU contents are reset and registers are initialized when the RST pin is pulled to low. s Initiating a Reset There are two methods to initiate a reset.
For the reset to be stable, the low pulse must be maintained for at least four clock cycles. However, it is important to minimize noise, since a reset may occur in a smaller number of clock cycles.
(1) Drive the RST pin low for at least four clock cycles. RST pin
4 clock cycles (200ns for a 20MHz oscillation) Figure 2-5-1 Minimum Reset Pulse Width (2) Set bit 7 (P2OUT7 flags) of the P2OUT register to "0." After reset is released, the P2OUT flag will be "1." s Releasing the Reset
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When the RST pin changes from low to high, an internal 15-bit counter begins counting at the oscillation clock frequency. The interval from when this counter begins counting until it overflows is known as the stabilization wait time. After waiting for this amount of time, the internal reset is released and the CPU begins operation.
RST pin Peripheral register
CPU internal reset
Oscillation stabilization wait time 215/fosc
Figure 2-5-2 Reset Release Sequence When returning from the STOP mode is terminating, the software can use the DLYCTR register to select an oscillation stabilization wait time of 0, 27/fosc, 211/fosc, or 215/fosc.
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Reset
Chapter 3
Port Functions
3
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37
Chapter 3 Port Functions
3-1 Overview
A total of 39 pins on the MN101C117, including those shared with special function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA. Each I/O port is assigned according to the special function register area in memory. I/O ports are operated in byte or bit units in the same way as RAM.
For each I/O port, the PnOUT register (port n output register) that sets the output value is assigned to memory address X'3F1n', and the PnIN register (port n input register) from which the input value is monitored is assigned to memory address X'3F2n'. * This I/O control is valid even when special functions are selected for the dual function pins.
*Table 3-1-1 Status When Port Is Reset (single-chip mode)
Port Port 0
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I/O Mode Input mode Input mode Input mode Input mode Input mode Input mode Input mode
Pull-up/Pull-down Resistor No pull-up resistor No pull-up resistor No pull-up resistor No pull-up resistor No pull-up/pull-down resistors No pull-up/pull-down resistors No pull-up/pull-down resistors
I/O Port or Special Function I/O port I/O port I/O port I/O port I/O port I/O port I/O port
Port 1 Port 2 Port 6 Port 7 Port 8 Port A
s Port 0 (P0) 4-bit CMOS tri-state I/O port. Table 3-1-2 Port 0 Functions
Pin Name Type P00 to P02 I/O P06
Dual Function SBO0(TXD), SBI0(RXD), SBT0 BUZZER
Description Each bit can be set individually as either an input or output by the P0DIR register. A pull-up resistor for each bit can be selected individually by the P0PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output).
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Overview
Chapter 3 Port Functions
s Port 1 (P1) 5-bit CMOS tri-state I/O port. Table 3-1-3 Port 1 Functions
Pin Name Type P10 to P14 I/O Dual Function Description RMOUT, Each bit can be set individually as either an input or TM2IO to TM4IO output by the P1DIR register. A pull-up resistor for each bit can be selected individually by the P1PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output).
s Port 2 (P2) 4-bit CMOS tri-state input port. Table 3-1-4 Port 2 Functions
Pin Name P20 to P23 Type Input Dual Function IRQ0, IRQ1(SENS), IRQ2 to 3 Description A pull-up resistor for each bit can be selected individually by the P2PLU register. At reset, the input mode pull-up resisters are disabled (high impedance output). Only 48-QFH has P23.
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s Port 6 (P6) 8-bit CMOS tri-state I/O port. Table 3-1-5 Port 6 Functions
Pin Name Type P60 to P67 I/O Dual Function Description Each bit can be set individually as either an input or output by the P6DIR register. A pull-up resistor for each bit can be selected individually by the P6PLU register. At reset, the input mode pull-up resisters are disabled (high impedance output).
Overview
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Chapter 3 Port Functions
s Port 7 (P7) 8-bit CMOS tri-state I/O port. Table 3-1-6 Port 7 Functions
Pin Name Type P70 to P71 I/O Dual Function Description Each individual bit can be switched to an input or output by the P7DIR register. A pull-up or pull-down resistor for each bit can be selected individually by the P7PLU register. However, pull-up and pull-down resistors cannot be mixed. At reset, the input mode pull-up resisters are disabled . 42-SDIP has no pins of P70,P71. 44-QFP has no pin of p71.
s Port 8 (P8) 8-bit CMOS tri-state I/O port. Table 3-1-7 Port 8 Functions
Pin Name
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Type
Dual Function LED0 to 7
P80 to P87 I/O
Description Each individual bit can be switched to an input or output by the P8DIR register. A pull-up resistor for each bit can be selected individually by the P8PLU register. When configured as outputs, it is possible to LED. At reset, when single chip mode is selected, the input mode pull-up resisters for P80 to P87 are disabled (high impedance output).
s Port A (PA) 8-bit CMOS tri-state input port. Table 3-1-8 Port A Functions
Pin Name Type PA0 to PA7 Input Dual Function Description AN0 to AN7 A pull-up or pull-down resistor for each bit can be selected individually by the PAPLUD register. However, pull-up and pull-down resistors cannot be mixed. At reset, the input mode pull-up resisters for PA0 to PA7 are disabled.
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Overview
Chapter 3 Port Functions
3-2 Port Control Registers
3-2-1 Overview
28 registers control the I/O ports. See table 3-2-1. Table 3-2-1 I/O Port Control Registers (1/2)
Name
P0OUT P1OUT P2OUT P6OUT P7OUT P8OUT P0IN
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Address
X'03F10' X'03F11' X'03F12' X'03F16' X'03F17' X'03F18' X'03F20' X'03F21' X'03F22' X'03F26' X'03F27' X'03F28' X'03F2A' X'03F30' X'03F31'
R/W
R/W R/W R/W R/W R/W R/W R R R R R R R R/W R/W
Function
Port 0 output register Port 1 output register Port 2 output register Port 6 output register Port 7 output register Port 8 output register Port 0 input register Port 1 input register Port 2 input register Port 6 input register Port 7 input register Port 8 input register Port A input register Port 0 direction control register Port 1 direction control register
P1IN P2IN P6IN P7IN P8IN PAIN P0DIR P1DIR
Port Control Registers
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Chapter 3 Port Functions
Table 3-2-1 I/O Port Control Registers (2/2)
Name
P6DIR P7DIR P8DIR P1OMD PAIMD P0PLU P1PLU P2PLU P6PLU P7PLUD P8PLU PAPLUD FLOAT1
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Address
X'03F36' X'03F37' X'03F38' X'03F39' X'03F3A' X'03F40' X'03F41' X'03F42' X'03F46' X'03F47' X'03F48' X'03F4A' X'03F4B'
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Function
Port 6 direction control register Port 7 direction control register Port 8 direction control register Port 1 output mode register Port A input mode register Port 0 pull-up control register Port 1 pull-up control register Port 2 pull-up control register Port 6 pull-up control register Port 7 pull-up/pull-down control register Port 8 pull-up control register Port A pull-up/pull-down control register Pin control register 1
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Port Control Registers
Chapter 3 Port Functions
7
P0OUT
6
P0OUT6
5
4
3
2
1
0
(at reset: -0---000)
P0OUT2 P0OUT1 P0OUT0
P1OUT
P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0
(at reset: ---00000)
P2OUT
P2OUT7
(at reset: 1-------)
P0IN
P0IN6
P0IN2 P0IN1 P0IN0
(at reset: -X---XXX)
P1IN
P1IN4 P1IN3 P1IN2 P1IN1 P1IN0
(at reset: ---XXXXX)
P2IN
P2IN2 P2IN1 P2IN0
(at reset: ----XXX)
P0DIR
P0DIR6
P0DIR2 P0DIR1 P0DIR0
(at reset: -0---000)
P1DIR
P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0
(at reset: ---00000)
P1OMD
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P14TCO P13TCO P12TCO
P10TCO
(at reset: ---00000)
P0PLU
P0PLU6
P0PLU2 P0PLU1 P0PLU0
(at reset: -0---000)
P1PLU
P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0
(at reset: ---00000)
P2PLU
P2PLU2 P2PLU1 P2PLU0
(at reset: -----000)
P6OUT
P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0
(at reset: 00000000)
P6IN
P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0
(at reset: XXXXXXXX)
P6DIR
P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0
(at reset: 00000000)
P6PLU
P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLU0
(at reset: 00000000)
Figure 3-2-1 Port Control Registers (1/2)
Port Control Registers
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Chapter 3 Port Functions
7
P7OUT
6
5
4
3
2
1
0
(at reset: - - - - - - 00)
P7OUT1 P7OUT0
P8OUT
P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0
(at reset: 00000000)
P7IN
P7IN1 P7IN0
(at reset: - - - - - - XX)
P8IN
P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0
(at reset: XXXXXXXX)
PAIN
PAIN7 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0
(at reset: XXXXXXXX)
P7DIR
P7DIR1 P7DIR0
(at reset: - - - - - - 00)
P8DIR
P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0
(at reset: 00000000)
PAIMD
PAAIN7 PAAIN6 PAAIN5 PAAIN4 PAAIN3 PAAIN2 PAAIN1 PAAIN0
(at reset: 00000000)
P7PLUD
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P7PLUD1 P7PLUD0
(at reset: - - - - - - 00)
P8PLU
P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLU0
(at reset: 00000000)
PAPLUD
PAPLUD7 PAPLUD6 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUD0
(at reset: 00000000)
Figure 3-2-1 Port Control Registers (2/2)
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Port Control Registers
Chapter 3 Port Functions
3-2-2 I/O Port Control Registers
This section describes the special function registers that control the MN101C117's I/O ports. s Data Registers * PnOUT registers Data registers to output to the ports. Data written to these registers is output from the ports. 0 1 Low (Vss level) is output. High (Vdd level) is output.
* PnIN registers Data registers to input data from the ports. The value of data at the pins can be input by reading these registers. These are read-only registers. 0 1
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Pin is low. Pin is high.
Input and output registers are mapped to separate addresses. To use these ports for I/O, configure them as I/O ports in the PnOMD/PnIMD registers, described in this section. s Direction Control Registers * PnDIR registers 0 1 Input mode Output mode
These registers set the port for use as an input or output. s Pull-up/Pull-down Resistor Control Registers * PnPLU registers These register settings determine whether internal pull-up resistors are added to the ports. 0 1 No pull-up / pull-down resistor Pull-up / Pull down resistor
* PnPLUD registers These register settings determine whether internal pull-up or pull-down resistors are added to the ports. 0 1 No pull-up / pull-down resistor Pull-up / Pull down resistor
Port Control Registers
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Chapter 3 Port Functions
s Port Output/Input Mode Registers * PnOMD/PnIMD registers These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used as I/O ports or as special function pins (dual function). If the special (dual) functions used, the PnDIR, PnPLU, PnPLUD, and other registers must be set. 0 1 I/O port Special function pin
Setting the PAIMD register prevents unnecessary current from flowing in a pin when an intermediate voltage (analog voltage) is applied to the pin.
s Pin Control Registers * FLOAT1 registers This register specifies whether the resistors-attached to pins P7 and PA are pull-up resistors or pull-down resistors. In addition, this register selects either zero cross input or Schmitt trigger input for pin P21.
7 FLOAT1 6 5 4 3 2 P21IM 1 0 (at reset: -----000)
PARDWN P7RDWN
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P7RDWN 0 1
P7 pull-up/pull-down resistor selection pull-up resistor pull-down resistor
PARDWN 0 1
PA pull-up/pull-down resistor selection pull-up resistor pull-down resistor
P21IM 0 1
P21 input mode selection Schmitt trigger input SENS input
Figure 3-2-2 Pin Control Register 1(FLOAT1: X'03F4B',R/W)
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Port Control Registers
Chapter 3 Port Functions
3-3 I/O Port Configuration and Functions
s P00,P02,P10 to P14
Reset Pull-up resistor control Write
R DQ L
Read
Reset I/O direction control Data bus Write
R DQ L
Read
Reset
R DQ
Port output data Write
L
Read Schmidt trigger input
Port input data Read Special function input data Special function output control Special function output data
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Pull-up resistor control I/O direction control Port output Port input Output format control
Special function input
Control bit Register (address) Control bit Register (address) Control bit Register (address) Control bit Register (address) Control bit Register (address)
Special function
P00 P02 P0PLU0 P0PLU2 P0PLU (X'03F40') P0DIR0 P0DIR2 P0DIR (X'03F30') P0OUT0 P0OUT2 P0OUT (X'03F10') P0IN0 P0IN2 P0IN (X'03F20') SC0SBOM SC0SBTM SC0MD3 (X'03F53') SBT0 SBO0(TXD) SBT0 SC0SBTS
P10 P1PLU0
P11 P1PLU1
P1DIR0
P1DIR1
P1OUT0
P1OUT1
P1IN0
P1IN1
P12 P1PLU2 P1PLU (X'03F41') P1DIR2 P1DIR (X'03F31') P1OUT2 P1OUT (X'03F11') P1IN2 P1IN (X'03F21')
P13 P1PLU3
P14 P1PLU4
P1DIR3
P1DIR4
P1OUT3
P1OUT4
P1IN3
P1IN4
TM2I RMOUT P10TCO TM2O P12TCO P1OMD (X'03F39') RMOUT RMOEN RMCTR (X'3F89)
TM3I TM3O P13TCO
TM4I TM4O P14TCO
Special function output control (1) Special function output control (2)
Special function
Control bit SC0SBOS Register (address) Special function Control bit Register (address)
SC0MD3 (X'03F53') SBO0/TXD SC0CMD SC0CTR (X'03F54')
Both The TM0RM flag of the RMCTR register and the P10TCO flag of the P10MD register are used to switch between remote control output and timer output.
I/O Port Configuration and Functions
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Chapter 3 Port Functions
s P01
Reset Pull-up resistor control Write
R DQ L
Read
Reset I/O direction control Write Data bus
R DQ L
Read
Reset
R DQ
Port output data Write
L
Read Schmitt trigger input
Port input data Read Special function input data
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Control bit Pull-up resistor Register control (address) Control bit I/O direction Register control (address) Control bit Port output Register (address) Control bit Port input Register (address) Special function input Special function
P01 P0PLU1 P0PLU (X'03F40') P0DIR1 P0DIR (X'03F30') P0OUT1 P0OUT (X'03F10') P0IN1 P0IN (X'03F20') SBI0/RXD
Figure 3-3-2 Configuration and Functions of P01
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I/O Port Configuration and Functions
Chapter 3 Port Functions
s PA0 to PA7
Reset
R DQ
Pull-up/pull-down resistor control Write
L
Read
Reset Pull-up/pull-down resistor selection
R DQ
Data bus
Write
L
Read Data bus Read
Read Port input data Reset Input mode control Write
R DQ L
Analog input
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PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Control bit PAPLUD0 PAPLUD1 PAPLUD2 PAPLUD3 PAPLUD4 PAPLUD5 PAPLUD6 PAPLUD7 Pull-up resistor Register PAPLUD control (address) (X'03F4A') Pull-up/ PARDWN Control bit pull-down Register FLOAT1 resistor (address) (X'03F4B') control Control bit PAAIN0 PAAIN1 PAAIN2 PAAIN3 PAAIN4 PAAIN5 PAAIN6 PAAIN7 Input mode Register PAIMD control (address) (X'03F3A') Control bit PAIN0 PAIN1 PAIN2 PAIN3 PAIN4 PAIN5 PAIN6 PAIN7 Port input Register PAIN (address) (X'03F2A') Special function Special function AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 input
Figure 3-3-3 Configuration and Functions of PA0 to PA7
I/O Port Configuration and Functions
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Chapter 3 Port Functions
s Pin Configuration for P20, P22 to P23
Reset Pull-up resistor control Write Data bus
R DQ L
Read
Schmitt trigger input Port input data Read Special function input data
*P23 is only for 48-pin package.
P23 P20 P22 Control bit P2PLU0 P2PLU2 P2PLU3 Pull-up resistor P2PLU Register control (X'03F42') (address) P2IN3 P2IN2 Control bit P2IN0 Port input P2IN Register (X'03F22') (address) Special function IRQ3 IRQ2 Interrupt input IRQ0 input Figure 3-3-4 Configuration and Functions of P20, P22, P23
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I/O Port Configuration and Functions
Chapter 3 Port Functions
s P21
Reset Pull-up resistor control Read Data bus
R DQ L
Read
Reset
R DQ
Special function input data
Read
L
Read
Port input data Read
Special function input data
AC zero-cross detection circuit
Schmitt trigger input
Pull-up resistor control Port input
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Control bit Register (address) Control bit Register (address)
Special function
Special function input selection
Control bit Register (address)
P21 P2PLU1 P2PLU (x'03F42') P2IN1 P2IN (x'03F22') SENS P21IM FLOAT1 (x'03F4B')
Figure 3-3-5 Configuration and Functions of P21
I/O Port Configuration and Functions
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Chapter 3 Port Functions
s P27
Schmitt trigger input Reset signal input Data bus Reset
S DQ
Port output data Write
L
Special input Special function output
Special function
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Control bit Register (address)
P27 RST Soft reset output P2OUT7 P2OUT (x'03F12')
Figure 3-3-6 Configuration and Functions of P27
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I/O Port Configuration and Functions
Chapter 3 Port Functions
s P70 to P71
Reset
Pull-up/pull-down resistor control Write
R DQ L
Read
Reset
Pull-up/pull-down resistor selection Write
R DQ L
Read
Reset Data bus
I/O direction control
R DQ
Write
L
Read
Reset
Port output data Write
R DQ L
Read
Port input data Read
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P70
Pull-up/ Control bit pull-down Register resistor control (address)
P71
P7PLUD0
P7PLUD (X'03F47') P7RDWN FLOAT1 (X'03F4B')
P7PLUD1
Control bit Pull-up/ pull-down Register resistor control (address) I/O direction control Port input Control bit Register (address) Control bit Register (address) Control bit Register (address)
P7DIR0
P7DIR (X'03F37')
P7DIR1
P7IN0
P7IN (X'03F27')
P7IN1 P7OUT1
P7OUT (X'03F17')
P7OUT0
Port output
Figure 3-3-7 Configuration and Functions of P70
I/O Port Configuration and Functions
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Chapter 3 Port Functions
sP60 to P67,P80 to P87
Reset Pull-up resistor control Write
R DQ L
Read
Reset I/O direction control Data bus Write
R DQ L
Read
Reset
R DQ
Port output data Write
L
Read
Schmidt trigger input Port input data Read
Pull-up resistor control I/O direction control
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Control bit Register (address) Control bit Register (address) Control bit Register (address) Control bit Register (address)
Port output
Port input
P65 P66 P67 P60 P61 P62 P63 P64 P6PLU0 P6PLU1 P6PLU2 P6PLU3 P6PLU4 P6PLU5 P6PLU6 P6PLU7 P6PLU (x'03F46') P6DIR0 P6DIR1 P6DIR2 P6DIR3 P6DIR4 P6DIR5 P6DIR6 P6DIR7 P6DIR (x'03F36') P6OUT0 P6OUT1 P6OUT2 P6OUT3 P6OUT4 P6OUT5 P6OUT6 P6OUT7 P6OUT (x'03F16') P6IN0 P6IN1 P6IN2 P6IN3 P6IN4 P6IN5 P6IN6 P6IN7 P6IN (x'03F26')
Figure 3-3-8 Configuration and Functions of P60 to P67
Pull-up resistor control I/O direction control Port output
Control bit Register (address) Control bit Register (address) Control bit Register (address) Control bit Register (address)
Port input
P85 P86 P87 P80 P81 P82 P83 P84 P8PLU0 P8PLU1 P8PLU2 P8PLU3 P8PLU4 P8PLU5 P8PLU6 P8PLU7 P8PLU (x'03F48') P8DIR0 P8DIR1 P8DIR2 P8DIR3 P8DIR4 P8DIR5 P8DIR6 P8DIR7 P8DIR (x'03F38') P8OUT0 P8OUT1 P8OUT2 P8OUT3 P8OUT4 P8OUT5 P8OUT6 P8OUT7 P8OUT (x'03F18') P8IN0 P8IN1 P8IN2 P8IN3 P8IN4 P8IN5 P8IN6 P8IN7 P8IN (x'03F28')
Figure 3-3-9 Configuration and Functions of P80 to P87
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I/O Port Configuration and Functions
Chapter 4
Timer Functions
4
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Chapter 4 Timer Functions
4-1 Overview
The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog timer, a time base timer, and circuits for remote control output and buzzer output.
Table 4-1-1 Summary of Timer Functions
Timer 2 (8-bit) Interrupt Timer operation Event counter Timer pulse output Serial transmission clock
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Timer 3 (8-bit) TM3IRQ
Timer 4 (16-bit) TM4IRQ
Timer 5 (8-bit) TM5IRQ
Time Base TBIRQ
TM2IRQ
x x x x x x fs fs/4 fx x fosc fs/4 fs/16 fosc fs/4 fs/16 x x x x x fosc fs/4 fx
x x x x x x fosc fx
PWM output Cascade connection Capture function 0 Clock source 1 2 3
TM2IO input TM3IO input TM4IO input fosc,fx/213 Remote control carrier pulse generation Pulse added type PWM Not possible to temporarily halt BC
Other
56
Overview
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TM3MD Read/Write
0
Read/Write
Compare register
Compare register
fs
Match
TM2OC
7
Match
MUX
8-bit counter 8-bit counter
TM3CK0 TM3CK1 TM3CK2 TM3PWM TM3EN - - -
TM3OC MUX MUX TM3BC R Read TM3IRQ
1/2
fs/4 MUX TM2BC R Read MUX
MUX
fx TM2IRQ
MUX
MUX
TM2IO input
Synchronization
TM3IO output/ PWM2/ Remote control carrier output/ Serial transfer clock output
1/2
Figure 4-1-1 Timers 2, 3 Block Diagram
MUX
RQ S
fosc f s/4 f s/16 TM3IO input MUX
Synchronization
MUX
TM2IO output/PWM2
TM2MD
TM2CK0 TM2CK1 TM2CK2 TM2PWM TM2EN - - -
0
RST input
Chapter 4 Timer Functions
7
Overview
57
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58
Read/Write Read/Write
16-bit compare register
Chapter 4 Timer Functions
Overview
TM4OCL
Pulse-added timing generation
TM4OCH
TM4PWM
Read
Match Match
Read MUX
TM4IRQ
R
fosc fs/4 fs/16 MUX
16-bit counter S Q
Pulse added MUX
1/2
TM4IO input
TM4BCL R
TM4BCH R Overflow of lower 8 bits
TCIO4Ioutput/ PWM output
MUX MUX RSTIO
Synchronization
16-bit capture register
Synchronization
TM4ICL Read Read
TM4ICH TM4MD
TM4CK0 TM4CK1 TM4CK2 T4ICT0 T4ICT1 TM4PWM TM4EN - 0
Figure 4-1-2 Timer 4 Block Diagram
7
IRQ0 IRQ1 IRQ2
MUX
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Read/Write
Compare register
TM5OC
Match
1min (32kHz),250ms (8.38MHz)
f s/4 MUX f osc Read fx MUX
Synchronization
TM5MD 0 TM5CK0 TM5CK1 TM5CK2 TM5CK3 TM5IR0 TM5IR1 TM5IR2 TM5CLRS 7
MUX TM5BC R
8-bit counter
TM5IRQ
MUX
f osc 1/2 250ms (32kHz) 0.977ms (8MHz) 1/2 1/2 1/2 1/2
7 8 9 10 13
MUX
TBIRQ MUX
fx 3.9ms, 7.8ms, 15.6ms, 31.2ms (32kHz)
Figure 4-1-3 Timer 5/Time Base Block Diagram
MUX
Chapter 4 Timer Functions
Overview
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60
Refer to the aragraph [1-6-1 ROM option]
Chapter 4 Timer Functions
Overview
WDCTR
0
Reset input
R
7
WDEN - - - - - - -
Internal reset release 1/2 6 fosc 1/2 10 fosc MUX 1/2 14 fosc ROM option
R S
fs
1/214
Overflow
R
1/4 DLYCTR 1/4 1/4
DLYS0 DLYS1 - - - BUZS0 BUZS1 BUZOE 0
Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram
1/212 1/211 1/210 1/29 MUX
Overflow
WDIRQ
7
Buzzer
Chapter 4 Timer Functions
Synchronization circuit
Remote control output
0
RMCTR
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1/2 duty
MUX
Figure 4-1-5 Remote Control Transmission Block Diagram
Timer 3 output
1/3 duty
- RMDTY0 - RMOEN - - - -
7
Overview
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Chapter 4 Timer Functions
4-2 8-bit Timer Operation (timers 2, 3)
4-2-1 Overview
Functions for timers 2 and 3 are listed below. Table 4-2-1 Summary of 8-bit Timer Functions
Timer 2 (8-bit) Interrupt Timer operation Event counter Timer pulse output Serial transmission clock PWM output Cascade connection Remote control carrier pulse generation Timer 3 (8-bit)
TM2IRQ TM3IRQ
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x
(SIF0)
x
x
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8-bit Timer Operation (timers 2, 3)
Chapter 4 Timer Functions
4-2-2 Operation
When servicing an interrupt, reset the timer 2 interrupt request flag before starting timer 2. During a count operation, be careful if the value set in TM2OC is smaller than the value of binary counter 2, since the count-up operation will continue until overflow occurs. If fx is to be selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized fx in order to avoid reading data that may be incomplete during countup transitions. However, with synchronized fx, it is not possible to return from STOP/HALT modes.
s Timer Operation (timers 2, 3) Settings for timer operation are listed below. Timer 2 is used as an example. (1) (2) (3) (4) (5) (6) (7) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set the TM2CK2 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronized fx as the clock source. Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is selected. Set a value in compare register 2 (TM2OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 (TM2BC) will count upward from X'00'. When the value of binary counter 2 matches that of the TM2OC register, the timer 2 interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count upward again.
? ? ? ? ? ?e?Y0@@4V? eY04V ? ?Y(@@3 ?e?5&OK) ?.O?@@ ?eH@J??L3? f@@ ?e5@f@N f@@ ?e@@f@3 f@@ @@ ?e@@f@@ f@@ ?e1@f@7 f@@ ?eL@N??H@J f@@N? ? e@@@@ ?e?1'IM(7? f@&*? ?e?X6@@2W? f&WW? ? ? ? ? ? ? ? ? ? ? ? ? ?
Clock
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TM4EN
Write to registers TM4OCH, TM4OCL
Binary counter 4
04
05
06
07
08
09
00
Figure 4-2-1 Binary Counter 2 (TM2BC) Count Timing If the TM2EN flag of TM2MD register is changed simultaneously with other bits, the switching operation may cause binary counter 2 to be incremented. If the value of TM2OC register is overwritten while timer 2 has stopped counting, binary counter 2 will be reset to X'00' at the edge of next count clock. The value of TM3CK0~2 of T3MD register is unsettled. If timer2/ timer 3 is independently used, any mode except cascade connection should be set.
8-bit Timer Operation (timers 2, 3)
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Chapter 4 Timer Functions
If TM2IO input is selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized TM2IO input to avoid reading data that may be incomplete during count-up transitions. However, with synchronized TM2IO input, it is not possible to return from STOP/HALT modes.
s Event Count Function (timers 2, 3) Settings for the event count function are listed below. Timer 2 is used as an example. (1) (2) (3) (4) (5) (6) (7) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Use the TM2CK2 to 0 flags of the TM2MD register to select TM2IO input or synchronous TM2IO input as the clock source. Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is selected. Set a value in compare register 2 (TM2OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 will count upward from X'00'. When the value of binary counter 2 matches that of the TM2OC register, the timer 2 interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count upward again.
When synchronized TM2IO is selected, the timer 2 clock source is synchronized with the system clock after a transition of the TM2IO input signal. Binary counter 2 counts upward based on a signal synchronized to the system clock. Therefore, correct values can be read from binary counter 2.
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CPU system clock (fs)
TM4IO input
Synchronous circuit output
Binary counter
n
n+1
Figure 4-2-2 Timer 2 Event Counter Timing (when synchronous TM2IO input is selected)
64
8-bit Timer Operation (timers 2, 3)
Chapter 4 Timer Functions
s Timer Pulse Output Function (timers 2, 3) Settings for the timer pulse output function are listed below. Timer 2 is used as an example. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set bit 2 of the port 1 output/input mode register (P1OMD) to "1" to set the special function pin. Bit 2 of port 1 will be specified as the pulse output pin. Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronized fx as the clock source. Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is selected. Set a value in compare register 2 (TM2OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 will count upward from X'00'. When the value of binary counter 2 matches that of the TM2OC register, the timer 2 interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count upward again.
Matches compare register
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The period of a signal output to the port is 1/2 of the period set in the TM2OC register. If port 1 is to be used as a pulse output pin, it is necessary to set the port 1 output direction control register (P1DIR) and the port 1 pull-up/pull-down resistor control register (P1PLU).
Binary counter
TM2OUT
Figure 4-2-3 Timer Pulse Output Timing
8-bit Timer Operation (timers 2, 3)
65
Chapter 4 Timer Functions
If the TM3PWM flag of the TM3MD register is set to "1" and timer 2 PWM output is selected, the PWM output of timer 2 will also be output from the TM3IO pin. If port 1 is to be used as a PWM output pin, the P1DIR and P1PLU registers must be set.
s PWM Output Function (Timer 2) Settings for the PWM output function are listed below. (1) (2) (3) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set bit 2 of the port 1 output/input mode register (P1OMD) to the special function pin setting. Bit 2 of port 1 will be specified as the PWM output pin. Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronous fx as the clock source. The period of the output waveform is determined based on the clock source. Set the TM2PWM flag of the TM2MD register to "1" so that PWM operation is selected. Set a value in compare register 2 (TM2OC). The high interval of the output waveform is determined based on the value of the TM2OC compare register. Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 will count upward from X'00'. A high-level signal is output from the port beginning when binary counter 2 starts counting at X'00' and ending when the value of binary counter 2 matches the value set in the TM2OC register. When the value of binary counter 2 matches that of the TM2OC register, a low-level signal is output from the port. Binary counter 2 continues to count upward until X'FF' is reached. At the next countup cycle, the value of binary counter 2 is reset to X'00', a high-level signal is output from the port, and counting begins again.
Overflow Matches TM2OC register Binary counter 2
(4) (5) (6) (7) (8)
(9)
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PWM output
Time specified by TM2OC register Time until binary counter 2 reaches X'FF'
Figure 4-2-4 PWM Output Timing
66
8-bit Timer Operation (timers 2, 3)
Chapter 4 Timer Functions
Clock
PWM output
Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00')
Matches TM2OC register Overflow
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Binary counter 2
PWM output
Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF')
8-bit Timer Operation (timers 2, 3)
67
Chapter 4 Timer Functions
The clock source for the serial interface has a frequency that is 1/2 of the overflow output of timer 3. For serial interface settings, refer to the chapter on serial functions.
s Serial Transfer Clock Function(timer 3) Settings for the serial transfer clock function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count operation of timer 3. Set the SC0CK1 and SC0CK0 flags of the serial interface 0 mode register 1 (SC0MD1) to select 1/2 of the timer 3 overflow frequency as the clock source. Set the TM3CK2 to 0 flags of the TM3MD register to select fosc, fs, fs/4, or fs/16 as the clock source. Set the TM3PWM flag of the TM3MD register to "0" to select timer 3 output. Set a value in compare register 3 (TM3OC). Set the TM3EN flag of the TM3MD register to "1" to start the timer. When timer 3 begins operation, binary counter 3 counts upward from X'00'. When the value of binary counter 3 matches that of the TM3OC register, the timer 3 interrupt request flag is set, the value of binary counter 3 is reset to X'00', and counting begins again.
s Cascade Connection Function (timer 2 + timer 3) Settings for the cascade connection function are listed below. Timer 2 and timer 3 are connected to operate as a 16-bit timer. (1) (2) (3) (4) (5) (6) (7) (8) (9)
Disable the timer 2 interrupt.
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Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count operation of timer 3. Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronized fx as the clock source. Use the TM3CK2 to 0 flags of the TM3MD register to set the clock source as a cascade connection with timer 2. Set the TM2PWM flag of the TM2MD register to "0" to select normal timer operation. Set values in compare register 2 (TM2OC) and compare register 3 (TM3OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. Set the TM3EN flag of the TM3MD register to "1" to start the timer. When timers 2 and 3 begin operation, the binary counters begin counting upward from X'0000' as a 16-bit counter. When the value of the 16-bit binary counter matches that of the 16-bit register (TM3OC+TM2OC), the timer 3 interrupt request flag is set, the value of the 16-bit binary counter is reset to X'0000', and counting begins again.
Use a 16-bit access instruction to set the (TM3OC+TM2OC) register.
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8-bit Timer Operation (timers 2, 3)
Chapter 4 Timer Functions
4-3 16-bit Timer Operation (timer 4)
4-3-1 Overview
Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin. An input capture function and pulse added type PWM output function can also be used.
4-3-2 Operation
s Timer Operation Settings for timer operation are listed below.
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When servicing an interrupt, reset the timer 4 interrupt request flag before operating timer 4. During a count operation, be careful if the value set in TM4OCH and TM4OCL is smaller than the value of binary counter 4, since the count-up operation will continue until overflow occurs.
(1) (2) (3) (4) (5) (6) (7)
Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Set the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Set the TM4PWM flag of the TM4MD register to "0" to select 16-bit timer operation. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 counts upward from X'0000'. When the value of binary counter 4 matches that of the TM4OCH and TM4OCL registers, the timer 4 interrupt request flag is set, the value of binary counter 4 is reset to X'0000', and counting begins again.
16-bit Timer Operation (timer 4)
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Chapter 4 Timer Functions
Clock
TM4EN
Write to registers TM4OCH, TM4OCL
Binary counter 4
04
05
06
07
08
09
00
Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing
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If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented. If the value of the TM4OCH, TM4OCL register is overwritten while timer 4 has stopped counting, binary counter 4 will be reset to X'0000'.
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16-bit Timer Operation (timer 4)
Chapter 4 Timer Functions
s Event Count Function Settings for the event count function are listed below. (1) (2) (3) (4) (5) (6) (7) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select TM4IO input or synchronized TM4IO input as the clock source. Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is selected. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'0000'. When the value of binary counter 4 matches that of the TM4OCH and TM4OCL registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to X'0000' and begins to count upward again.
If TM4IO input is selected as the clock source and the value of binary counter 4 is to be read during operation, select synchronized TM4IO input to avoid reading data that may be incomplete during count-up transitions. However, with synchronized TM4IO input, it is not possible to return from STOP/HALT modes.
When synchronized TM4IO is selected, the timer 4 clock source is synchronized with the system clock after a transition of the TM4IO input signal. Timer 4 counts upward based on a signal synchronized to the system clock. Therefore, correct values can be read from binary counter 4.
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Figure 4-3-2 Timer 4 Event Counter Timing (when synchronous TM4IO
CPU system clock (fs)
TM4IO input
Synchronous circuit output
Binary counter
n
n+1
input is selected)
16-bit Timer Operation (timer 4)
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Chapter 4 Timer Functions
The period of the output signal from the port is 1/2 of the period set in the TM4OCH, TM4OCL register.
s Timer Pulse Output Function Settings for the timer pulse output function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count operation of timer 4 is stopped. Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function pin setting. Bit 4 of port 1 will be specified as the pulse output pin. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is selected. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'0000'. When the value of binary counter 4 matches that of the TM4OCH and TM4OCL registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to X'0000' and begins to count upward again.
Matches TM4OCH, TM4OCL register
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Binary counter 4
TM4OUT
Figure 4-3-3 Timer Pulse Output Timing
72
16-bit Timer Operation (timer 4)
Chapter 4 Timer Functions
s Pulse Added Type PWM Output Function In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit PWM output. Precise control is possible based on the number of PWM repetitions (256 times) to which this bit is appended. Settings for the pulse added type PWM output function are listed below. (1) (2) (3) (4) (5) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function pin setting. Bit 4 of port 1 will be specified as the PWM output pin. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. The period of the output waveform is determined based on the clock source. Set the TM4PWM flag of the TM4MD register to "1" so that PWM operation is selected. Set a value in the lower 8 bits of compare register 4 (TM4OCL). The high interval of the output waveform is determined based on the value of the lower 8 bits of compare register 4 (TM4OCL). Set the position of the added pulse in the upper 8 bits of compare register 4 (TM4OCH). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'00'. A high-level signal is output from the port beginning when binary counter 4 starts counting from X'00' and ending when the value of binary counter 4 matches the value set in the TM4OCL register. When the value of binary counter 4 matches that of the TM4OCL register, a lowlevel signal is output from the port. Binary counter 4 continues to count upward until X'FF' is reached. At the next countup cycle, the value of binary counter 4 is reset to X'00', and counting begins again. A high-level signal is output from the port. Use a 16-bit access instruction to set the TM4OCH, TM4OCL register.
If bit 4 of port 1 is to be used as a PWM output pin, set the P1DIR and P1PLU registers.
(6) (7) (8) (9)
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PWM4 output is fixed at L with X'FF' set at the lower 8 bits(TM40CL) of compare register. Use of timer 4 at PWM mode disables setting of X'FF' att TM4OCL register.
(10) (11)
Tn=X'00'
,, ,, ,,
Tn=X'01'
Basic PWM components
Added pulse
Tn=X'02'
Repeated 256 times
,
Tn=X'03'
Tn=X'04'
,, ,, ,
Tn=X'FF'
: Added pulse
Figure 4-3-4 Pulse Added Type PWM Output
16-bit Timer Operation (timer 4)
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Chapter 4 Timer Functions
[ 5-2-3 "Serial Interface Transfer Timing"]
s Setting the Added Pulse Position The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse. If the TM4OCH register is set to X'00', an additional bit is not appended to the basic PWM component. If the TM4OCH register is set to X'FF', an additional bit is repeatedly appended to the 255 basic PWM components during the period. The relation between the value set in the TM4OCH register and the added pulse is shown in the table below. If X'03' is set in the TM4OCH register, bits are appended to pulse positions for X'01' and X'02', shown in table 4-3-1. The relation between the value set in the TM4OCH register and the position of the added bit is shown in figure 4-3-5. Table 4-3-1 Pulse-Added PWM OutputFigure
Value Set in TM4OCH Register Added Pulse Position (value of Tn)
00000000 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000
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X'80' X'40',X'C0' X'20',X'60',X'A0',X'E0' X'10',X'30',X'50',X'70',X'90',X'B0',X'D0',X'F0' X'08',X'18',X'28',X'38',X'48',X'58' . . . . .,X'E8',X'F8' X'04',X'0C',X'14',X'1C',X'24',X'2C' . . . . .,X'F4',X'FC' X'02',X'06',X'0A',X'0E',X'12',X'16' . . . . .,X'FA',X'FE' X'01',X'03',X'05',X'07',X'09',X'0B' . . . . .,X'FD',X'FF'
(MSB)
(LSB)
Repeated 256 times
X '40' X '80' X 'C0' X 'FF'
TM4OCH Register setting 0 value X '00' X '01' X '02' X '04' X '08' X '10'
Position of added pulse
PWM basic component Position of added pulse X'87' Position of added pulse X'88'
Figure 4-3-5 Pulse Added Type PWM Output
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16-bit Timer Operation (timer 4)
Chapter 4 Timer Functions
s Capture Function Settings for the capture function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) (9) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Use the T4ICTS1 and T4ICTS0 flags of the TM4MD register to select IRQ2, IRQ1, or IRQ0 as the input capture trigger. Set the REDGn flag of the external interrupt control register to specify the valid edge for the interrupt selected as the TM4 input capture trigger. Set the TM4PWM flag of the TM4MD register to "1" to select 16-bit timer operation. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'0000' until it reaches the value set in compare register 4. If the binary counter is to be used as a free-running counter that counts from X'0000' to X'FFFF', set the compare register 4 to X'FFFF'. When the value of binary counter 4 matches that of the TM4OCH, TM4OCL register, the timer 4 interrupt request flag is set, binary counter 4 is reset to X'0000', and counting begins again. If the external interrupt selected as the TM4 input capture trigger is received during timer 4 operation, the value of binary counter 4 will be written into the input capture register (TM4ICH, TM4ICL).
Setting a value in compare register 4, clears binary counter 4.
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If the event occurs before a read, that data will be overwritten.
16-bit Timer Operation (timer 4)
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Chapter 4 Timer Functions
4-4 8-bit Timer Operation (timer 5)
4-4-1 Overview
Timer 5 is an 8-bit timer that can have fosc, fs/4, fx, or time base output as its clock source.
4-4-2 Operation
s Timer Operation Settings for timer operation are listed below. (1) Set the TM5CLRS flag of the timer 5 mode register (TM5MD) to "0." (2) Use the TM5CK3 to 1 flags of the TM5MD register to select fosc, fs/4, fx, synchronized fx, time base timer output, or time base timer synchronized output as the clock source. (3) Set a value in compare register 5 (TM5OC). At this time, if the TM5CLRS flag is "0," binary counter 5 will be initialized to X'00'. (4) Binary counter 5 (TM5OC) counts upward from X'00'. (5) When the value of binary counter 5 matches that of the TM5OC register, the timer 5 interrupt request flag is set, the binary counter is reset to X'00', and counting begins again.
When servicing an interrupt, reset the timer 5 interrupt request flag before starting timer 5.
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When choosing either time base timer output or time base timer synchronized output for the timer 5 clock source, the time base must be set up. During a count operation, be careful if the value set in TM5OC is smaller than the value of binary counter 5, since the count-up operation will continue until overflow occurs. If fx input is selected as the clock source and the value of binary counter 5 is to be read during operation, select synchronized fx input to avoid reading data that may be incomplete during countup transitions. However, with synchronized fx input, it is not possible to return from STOP/HALT modes.
If the TM5CLRS flag of the TM5MD register is set to "0," binary counter 5 will be initialized every time data in the TM5OC register is overwritten. Timer 5 interrupts are disabled in this mode. If timer 5 interrupts are to be used, the TM5CLRS flag must be reset to "1" after writing to the TM5OC register.
Timer 5 operation cannot be halted.
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8-bit Timer Operation (timers 2, 3)
Chapter 4 Timer Functions
4-5 Time Base Operation
4-5-1 Overview
The clock source for the time base timer can be set to fosc or fx. Also, the interrupt period for time base timer (TBIRQ) can be set to 1/27, 1/28, 1/29, 1/210, or 1/213 of the clock source.
4-5-2 Operation
s Time Base Function Settings for the time base function are listed below. (1)
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(2) (3)
Use the TM5CK0 flag of the timer 5 mode register (TM5MD) to select fosc or fx as the clock source. Use the TM5IR2 to 0 flags of the TM5MD register to select the time base timer interrupt source. When the selected time interval passes, the interrupt request flag of the time base interrupt control register (TBICR) is set.
Time base operation cannot be halted.
Table 4-5-1 Base Time Settings
TM5IR2 to 0 Clock Source 20MHz fosc 8.38MHz fx 32.768kHz 15.2s 3.9ms 30.5s 7.8ms 61.0s 15.6ms 122.0s 31.2ms 976.4s 250ms 000
1 27
001
1 28
010
1 29
011
1 210
1XX
1 213
6.4s
12.8s
25.6s
51.2s
409.6s
Time Base Operation
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Chapter 4 Timer Functions
4-6 Watchdog Timer Operation
4-6-1 Overview
The watchdog timer is controlled by the watchdog control register (WDCTR) and can be used for runaway program detection.
4-6-2 Setup and Operation
(1)
The upper 2 bits of the watchdog timer are cleared when the WDEN flag is set to "0." Therefore, if WDEN flag is set to 0 when an uppermost bit of a watchdog timer is 1, WDT interrupt occurs depending on the timing of this clear the watchdog timer may be reset at 1/4TWD. If the WDEN bit is to be repeatedly cleared and set at regular intervals, those operations should be performed within 1/4 of the TWD period.
(2)
Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start the watchdog timer. Operate the watchdog timer by clearing the WDEN flag to "0" within the fixed amount of time (TWD), and then resetting the WDEN flag to "1." If the WDEN flag is not cleared, a WDT interrupt will be generated after the fixed amount of time passes. When an illegal operation is detected, the program encoded at the location of the WDT interrupt routine is executed.
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TWD is set by the ROM option as fs/216, fs/218, or fs/220. Illegal operation detection period vs. WDEN clear period is shown by the following formula: Illegal operation detection period > [WDEN clear period] x 4
When software resetting is not triggered by WDT interrupt, hardware resetting (low level output at the reset terminal) takes place at the next WDT interrupt.
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Watchdog Timer Operation
Chapter 4 Timer Functions
4-7 Remote Control Output Operation
4-7-1 Overview
A remote control carrier pulse can be generated using the overflow of timer 3. Two duty ratios of 1/2 or 1/3 can be selected.
4-7-2 Setup and Operation
(1) (2) (3) (4) (5)
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Set the RMOEN flag of the remote control carrier output control register (RMCTR)to "0" so that the remote control carrier output is switched off. Set timer 3 to select the base period of the remote control carrier (the width that the remote control carrier output pulse is held at a high level). Set the RMDTY0 flag of the RMCTR register to select the carrier duty. Set the P10 output data to "0" and set P10 to the output mode. And select the remote control carrier output by setting the TMORM flag of the RMCTR register to "0". The RMOEN flag of the RMCTR register controls whether the remote control carrier output is on or off. Even if the carrier output is at a high level, and the RMOEN flag is set to "0" (off), the carrier waveform will be maintained by the synchronous circuit
Set bit 0 of the P1OMD register to "1" at the same time the remote control output is switched on, and to "0" at the same time the remote control output is switched off.
Base period set by TM3 RMOEN Output on Output off
RMOUT (1/3 duty)
Figure 4-7-1 Remote Control Carrier Output Waveform
Remote Control Output Operation
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Chapter 4 Timer Functions
4-8 Buzzer Output
4-8-1 Buzzer Output Setup and Operation
The square wave having a frequency 1/29 to 1/212 of the system clock can be output from the P06/BUZZER pin. (1) (2) (3) (4) Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR) to "0" so that the buzzer output is turned off. Set the buzzer output frequency with the BUZCK1 and BUZCK0 flags of the DLYCTR. Set the BUZOE flag of the DLYCTR register to "1" and set P06 to the buzzer output mode. The BUZOE flag of the DLYCTR register controls whether the buzzer output is ON or OFF.
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Buzzer Output
Chapter 4 Timer Functions
4-9 Timer Function Control Registers
4-9-1 Overview
19 registers control the timers. See table 4-9-1. Table 4-9-1 Timer Control Registers Name
TM2OC TM2BC TM2MD TM3OC TM3BC TM3MD TM4OCL TM4OCH TM4BCL TM4BCH
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Address
X'03F72' X'03F62' X'03F82' X'03F73' X'03F63' X'03F83' X'03F74' X'03F75' X'03F64' X'03F65' X'03F66' X'03F67' X'03F84' X'03F78' X'03F68' X'03F88' X'03F02' X'03F03' X'03F89'
R/W
R/W R R/W R/W R R/W R/W R/W R R R R R/W R/W R R/W R/W R/W R/W Binary counter 2
Function
Compare register 2 Timer 2 mode register Compare register 3 Binary counter 3 Timer 3 mode register Compare register 4 (lower 8 bits) Compare register 4 (upper 8 bits) Binary counter 4 (lower 8 bits) Binary counter 4 (upper 8 bits) Input capture register (lower 8 bits) Input capture register (upper 8 bits) Timer 4 mode register Compare register 5 Binary counter 5 Timer 5 mode register Watchdog timer control register Oscillation stabilization wait control register Remote control carrier output control register
TM4ICL TM4ICH TM4MD TM5OC TM5BC TM5MD WDCTR DLYCTR RMCTR
R/W: Readable and writable R: Read only
Overview
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4-9-2 Programmable Timer/Counters
Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4). Programmable timer/counters consist of a compare register and a binary counter.
(1) Compare register 2 (TM2OC) 7 6 5 4 3 2 1 0
(at reset: undefined)
TM2OC7 TM2OC6 TM2OC5 TM2OC4 TM2OC3 TM2OC2 TM2OC1 TM2OC0
Figure 4-9-1 Compare Register 2 (TM2OC: X'03F72', R/W) (2) Binary counter 2 (TM2BC) 7 6 5 4 3 2 1 0
(at reset: 00000000)
TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0
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Figure 4-9-2 Binary Counter 2 (TM2BC: X'03F62', R) (3) Compare register 3 (TM3OC) 7 6 5 4 3 2 1 0
(at reset: undefined)
TM3OC7 TM3OC6 TM3OC5 TM3OC4 TM3OC3 TM3OC2 TM3OC1 TM3OC0
Figure 4-9-3 Compare Register 3 (TM3OC: X'03F73', R/W) (4) Binary counter 3 (TM3BC) 7 6 5 4 3 2 1 0
(at reset: 00000000)
TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0
Figure 4-9-4 Binary Counter 3 (TM3BC: X'03F63', R)
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(5) Compare register 4 (TM4OCL) (lower 8 bits) 7 6 5 4 3 2 1 0
(at reset: undefined)
TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCL0
Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W) (6) Compare register 4 (TM4OCH) (upper 8 bits) 7 6 5 4 3 2 1 0
(at reset: undefined)
TM4OCH7 TM4OCH6 TM4OCH5 TM4OCH4 TM4OCH3 TM4OCH2TM4OCH1 TM4OCH0
Figure 4-9-6 Compare Register 4 (TM4OCH: X'03F75', R/W) (7) Binary counter 4 (TM4BCL) (lower 8 bits) 7 6 5 4 3 2 1 0
(at reset: 00000000)
TM4BCL7 TM4BCL6 TM4BCL5 TM4BCL4 TM4BCL3 TM4BCL2 TM4BCL1 TM4BCL0
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Figure 4-9-7 Binary Counter 4 (TM4BCL: X'03F64', R) (8) Binary counter 4 (TM4BCH) (upper 8 bits) 7 6 5 4 3 2 1 0
(at reset: 00000000)
TM4BCH7 TM4BCH6 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2 TM4BCH1 TM4BCH0
Figure 4-9-8 Binary Counter 4 (TM4BCH: X'03F65', R)
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(9) Input capture register (TM4ICL) (lower 8 bits) 7 6 5 4 3 2 1 0
(at reset: undefined)
TM4ICL7 TM4ICL6 TM4ICL5 TM4ICL4 TM4ICL3 TM4ICL2 TM4ICL1 TM4ICL0
Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R) (10) Input capture register (TM4ICH) (upper 8 bits) 7 6 5 4 3 2 1 0
(at reset: undefined)
TM4ICH7 TM4ICH6 TM4ICH5 TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICH0
Figure 4-9-10 Input Capture Register (TM4ICH: X'03F67', R) (11) Compare register 5 (TM5OC) 7 6 5 4 3 2 1 0
(at reset: undefined)
TM5OC7 TM5OC6 TM5OC5 TM5OC4 TM5OC3 TM5OC2 TM5OC1 TM5OC0
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Figure 4-9-11 Compare Register 5 (TM5OC: X'03F78', R/W) (12) Binary counter 5 (TM5BC) 7 6 5 4 3 2 1 0
(at reset: 00000000)
TM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0
Figure 4-9-12 Binary Counter 5 (TM5BC: X'03F68', R)
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4-9-3 Timer Mode Registers
Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and the time base. (1) Timer 2 mode register (TM2MD)
7 TM2MD - 6 - 5 - 4 TM2EN 3 2 1 0 (at reset: ---00XXX)
TM2PWM TM2CK2 TM2CK1 TM2CK0
TM2CK2 TM2CK1 TM2CK0 X 0 1 0 1 1 0 1 0 1 0 1
Clock source selection fs fs/4 fx * TM2IO input Synchronous fx * Synchronous TM2IO input
* 48QFH package only
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TM2PWM 0 1
TM2 operation mode selection Normal timer operation PWM operation
TM2EN 0 1
TM2 count control Halt the count Operate the count
Figure 4-9-13 Timer 2 Mode Register (TM2MD: X'03F82', R/W)
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(2) Timer 3 mode register (TM3MD)
7 TM3MD - 6 - 5 - 4 3 2 1 TM3CK1 0 TM3CK0 (at reset: ---00XXX)
TM3EN TM3PWM TM3CK2
TM3CK2
TM3CK1 0
TM3CK0 0 1 0 1 x 1
Clock source selection fosc fs/4 fs/16 TM3IO input Cascade connection with timer 2 Synchronous TM3IO input
0 1 1 0 1
TM3PWM 0 1
P13 output selection during TM2 PWM operation Timer 3 output Timer 2 PWM output
TM3EN
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TM3 count control Halt the count Operate the count
0 1
Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W)
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(3) Timer 4 mode register (TM4MD)
7 TM4MD - 6 TM4EN 5 4 3 T4ICTS0 2 TM4CK2 1 TM4CK1 0 TM4CK0 (at reset: -0000XXX)
TM4PWM T4ICTS1
TM4CK2
TM4CK1 0
TM4CK0 0 1 0 1 1
Clock source selection fosc fs/4 fs/16 TM4IO input Synchronous TM4IO input
0 1 1 1
T4ICTS1 0 1
T4ICTS0 0 1 0 1
TM4 input capture trigger selection Disable input capture operation IRQ0 IRQ1 IRQ2
TM4PWM
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TM4 operation mode selection 16-bit timer operation PWM operation
0 1
TM4EN 0 1
TM4 count control Halt the count Operate the count
Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W)
Timer Function Control Registers
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(4) Timer 5 mode register (TM5MD)
7 TM5MD
6
5 TM5IR1
4 TM5IR0
3 TM5CK3
2 TM5CK2
1 TM5CK1
0 TM5CK0 (at reset: 0XXXXXX0)
TM5CLRS TM5IR2
TM5CK0 0 1
Time base timer clock source selection fosc (Use Prohibited) fx * * 48QFH package only
TM5CK3 TM5CK2 X 0 1 1 0
TM5CK1 Timer 5 clock source selection 0 1 0 1 0 1 fosc fs/4 (Use Prohibited) Output of time base timer (Use Prohibited) Synchronous time base timer output
TM5IR2
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TM5IR1 0
Time base timer TM5IR0 interrupt period selection 0 1 0 1 x 1/27 of the clock source 1/28 of the clock source 1/29 of the clock source 1/210 of the clock source 1/213 of the clock source
0 1 1 x
TM5CLRS 0 1
Binary counter 5 clear selection flag Enable initialization of TM5BC during a write to TM5OC Disable initialization of TM5BC during a write to TM5OC
If TM5CLRS=0, TM5IRQ is disabled.
Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W)
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4-9-4 Timer Control Registers
(1) Watchdog timer control register (WDCTR)
7 WDCTR - 6 - 5 - 4 - 3 - 2 - 1 - 0 WDEN (at reset: -------0)
WDEN 0 1
Watchdog timer enable Clear watchdog timer/disable operation Enable WDT timer
Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W)
(2) Oscillation stabilization wait control register (DLYCTR)
7
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6
5
4 -
3 -
2 -
1
0 (at reset: 0XX---00)
DLYCTR
BUZOE BUZCK1 BUZCK0
DLYS1 DLYS0
DLYS1 DLYS0 0 1 1 0 1 0 1
Oscillation stabilization wait period setting 1/214 of the system clock (fs) 1/210 of the system clock (fs) 1/26 of the system clock (fs) Disable use
After reset is released, the oscillation stabilization wait period is fixed at 1/215. BUZCK1 BUZCK0 0 1 0 1 0 1 Buzzer output frequency selection 1/212 of the system clock (fs) 1/211 of the system clock (fs) 1/210 of the system clock (fs) 1/29 of the system clock (fs)
BUZOE P06 output selection 0 1 P06 port output P06 buzzer output
Figure 4-9-18 Oscillation Stabilization Wait Counter Control Register (DLYCTR: X'03F03', R/W)
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(3) Remote control carrier output control register (RMCTR)
7 RMCTR - 6 - 5 - 4 - 3 RMOEN 2 - 1 RMDTY0 0 - (at reset: ---00XX0)
Must be set to "0."
RMDTY0 0 1
Remote control carrier output duty selection 1/2 duty 1/3 duty
Must be set to "0."
RMOEN 0 1
Enable remote control carrier output Output low level Output remote control carrier
Must be set to "0."
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Figure 4-9-19 Remote Control Carrier Control Register (RMCTR: X'03F89', R/W)
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Chapter 5
Serial Functions
5
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5-1 Overview
The MN101C117 contains a serial interface that can operate in synchronous and simple UART modes. An overview of serial functions is shown below.
Table 5-1-1 Overview of Serial Functions
Serial 0 Interrupt Synchronous Simple UART fs/2 fs/4 fs/16 BC3X1/2 External SC0ICR
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Clock selection
1/8 period of clock
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SC0MD3
0
SC0MD2
8 8
0
SWAP SC0RXB 8
7
SC0SBTS SC0SBIS SC0SBOS SC0SBTM SC0SBOM SC0IOM - -
Stop bit detection Receive buffer
8 SC0TRB 8
7
SC0NPE SC0PM0 SC0PM1 SC0FM0 SC0FM1 SC0BRKE - -
SBO0/P00 M U X Shift register Start condition transmission Break receive control Start condition detection
Receive Append control transmit parity check control parity
SBO0/TXD1/P00
SBI0/RXD/P01
SBT0/P02 Bit counter
M U X 3 M U X
SC0IRQ
ORE detection control
Figure 5-1-1 Serial 0 Block Diagram
SC0MD1
0 SC0LNG0 SC0LNG1 SC0LNG2 SC0STE SC0DIR SC0CE0 SC0CE1 - 7
M U X
fs/2 fs/4 fs/16 BC3x1/2 1/2 of timer 3 overflow SC0MD0 0
SC0TRI SC0ERE SC0BRKF SC0CK0 SC0CK1 SC0CKM - - 7
SC0CTR
- SC0ORE SC0PEK SC0FEF - - SC0CMD SC0BSY
0
2
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Overview
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5-2 Synchronous Serial Interface
5-2-1 Overview
A serial interface begins operation when data is written to the shift buffer. A bit counter is incremented at each 1-bit transfer. The transfer is complete when the counter overflows. Bit transfers of an arbitrary 1 to 8 bits can be performed. The transfer bit count must be set before performing the transfer.
5-2-2 Setup and Operation
s Transmission
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(1) (2)
(3) (4)
[ Section 5-2-3, "Serial
(5) (6)
Interface Transfer Timing"]
Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as 1 to 8 bits. Specify whether the start condition is enabled or disabled with the SC0STE flag of the SC0MD0 register. Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the SC0MD0 register. Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. When the clock source is an internal clock: * Select the clock source with the SC0CK1 to 0 flags of serial interface 0 mode register 1 (SC0MD1). * Set the SC0CKM flag of the SC0MD1 register specify whether or not the clock source frequency will be divided by 8. * Select serial clock operation by setting the SC0SBTS flag of the serial interface 0 mode register 3 (SC0MD3) to "1." * Set the SC0SBTM flag of the SC0MD3 register. * Set bit 0 of the port 0 direction control register (P0DIR) to the output mode. * Set bit 0 of the port 0 pull-up resistor control register (P0PLU).
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When the clock source is an external clock (SBT0 pin input): * Set the SC0SBTM flag of the SC0MD3 register. * Set bit 2 of the P0DIR register to input mode. * Set the P0PLU register, if necessary. Select the SC0SBOM flag of the SC0MD3 register. Select the SC0IOM flag of the SC0MD3 register. Select serial communication by setting the SC0SBOS flag of the SC0MD3 register to "1." Set transmit data to serial interface 0 transmit/receive shift register (SC0TRB). This will start the serial transmission. When serial transmission begins, the SC0BSY flag of the SC0CTR register is set to "1," indicating that a serial transfer is in progress. When the serial transmission has completed, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of SC0MD1 register 1 is cleared to "0."
(7) (8) (9) (10) (11) (12)
When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are changed, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register may be incremented. Enabling the start condition drives the SBO0 pin high for a fixed time interval (1/2 the clock source cycle) after the transmission is completed. If the start condition is disabled, the SBO0 pin will remain at the value of the of the last data bit. If the SC0IOM flag of the SC0MD3 register is set for a pin connection, the SBI0 pin can be used as a port. The SBO0 pin receives data during the input mode and transmits data during the output mode.
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After the transfer is complete, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register will be changed. Except in an 8-bit transfer, reset the transfer bit count at the time of the next transmission.
When switching from transmission to reception, set the SC0SBOS flag of the SC0MD3 register to "0" and then set the SC0SBIS flag to "1." Do not change both of these flags at the same time.
The SC0LNG2 to 0 flags change at the opposite edge of the transmit data output edge.
The SC0SBTS flag of the SC0MD3 register must be set to "1" before the SC0SBOS flag of the SC0MD3 register is set to "1."
Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set.
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SBT Clock
ts
SBO Start condition enabled SBO Start condition disabled
Interrupt
SC0BSY SC0LNG2 to 0 0 1 2 3 4 5 6 7 0
Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge)
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Clock SBT SBO Start condition enabled SBO Start condition disabled
Interrupt
SC0BSY
SC0LNG2 to 0
0
1
2
3
4
5
6
7
0
Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge)
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s Reception (1) (2) Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as 1 to 8 bits. Specify whether the start condition is enabled or disabled with the SC0STE flag of the SC0MD0 register. Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the SC0MD0 register. Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. When the clock source is an internal clock: * Select the clock source with the SC0CK1 to 0 flags of serial interface 0 mode register 1 (SC0MD1). * Set the SC0CKM flag of the SC0MD1 register to specify whether or not the clock source frequency will be divided by 8. * Select serial clock pin operation by setting the SC0SBTS flag of the serial interface 0 mode register 3 (SC0MD3) to "1." * Set the SC0SBTM flag of the SC0MD3 register. * Set bit 2 of the port 0 direction control register (P0DIR) to the output mode (P02/SBT0 output mode). * If necessary, set bit 2 of the port 0 pull-up resistor control register (P0PLU) to add the pull-up resistor. When the clock source is an external clock (SBT0 pin input): * Set bit 2 of the P0DIR register to the input mode. * If necessary, set bit 2 of the P0PLU register. Select the SC0IOM flag of the SC0MD3 register. Select serial communication by setting the SC0SBIS flag of the SC0MD3 register to "1." (Reception data wait.) When the serial reception begins, the SC0BSY flag of the serial interface 0 control register (SC0CTR) is set to "1," indicating that a serial transfer is in progress. When the serial reception is complete, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of the SC0MD1 register is set to "1." After the transfer is complete, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register will be changed. Except in an 8-bit transfer count, reset the transfer bit count at the time of the next reception. When switching from reception to transmission, set the SC0SBIS flag of the SC0MD3 register to "0" and then set the SC0SBOS flag to "1." Do not change both of these flags at the same time.
When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are changed, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register may by incremented.
(3) (4) (5) (6)
[
Section 5-2-3, "Serial
Interface Transfer Timing"]
If the start condition is enabled, the SC0LNG2 to 0 flags of the SC0MD0 register will be cleared when the start condition is received. In this case, the receive bit count is fixed at 8 bits. The SC0SBTS flag of the SC0MD3 register must be set to "1" before setting the SC0SBIS flag of the SC0MD3 register to "1."
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(7) (8) (9)
(10)
If the internal clock is selected as the clock source, after setting the SC0SBIS flag of the SC0MD3 register to "1," write dummy data to the SC0TRB register. If there is to be another reception, write dummy data again to the SC0TRB register. The SC0LNG2 to 0 flags change at the opposite edge of the transmit data output edge. Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set.
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Clock
Start condition enabled
Start condition disabled
Interrupt SC0BSY start condition enabled SC0BSY start condition disabled
SC0LNG2 to 0
0
1
2
3
4
5
6
7
0
Figure 5-2-3 Synchronous Serial Interface Reception Timing (reception at rising edge)
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Clock
Start condition enabled
Start condition disabled
Interrupt SC0BSY start condition enabled SC0BSY start condition disabled SC0LNG2 to 0
0
1
2
3
4
5
6
7
0
Figure 5-2-4 Synchronous Serial Interface Reception Timing (reception at falling edge)
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5-2-3 Serial Interface Transfer Timing
Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode register 0 (SC0MD0), to control the edge at which transmission data is output and the edge at which reception data is input. During transmission, when the SCnCE1 flag is "0," data output is synchronized to the falling edge of the clock. During reception, when the SCnCE0 flag is "0," data reception is synchronized to the opposite polarity edge of the transmit data edge. When the SCnCE0 flag is "1," data reception is synchronized to the same polarity edge as the transmit data edge. Table 5-2-1 Serial Data Input Edge and Output Edge (serial interface 0)
SC0CE0 SC0CE1
Receive Data Input Edge
Transmit Data Output Edge
0
0
0
1
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0
1
1
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When serial interface 0 is used for simultaneous transmission and reception, set the SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the reception data input edge is opposite in polarity to the transmit data output edge. Also, the polarity of the reception data input edge is opposite polarity of the transmit data output edge of the other device.
SBT0
Data is input in synchronization with the rising edge of the clock.
SBI0
Data is output in synchronization with the falling edge of the clock. SBO0
Figure 5-2-5 Synchronous Serial Transmit/Receive Timing (data is received at the rising edge and transmitted at the falling edge)
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SBT0
Data is input in synchronization with the falling edge of the clock.
SBI0
Data is output in synchronization with the rising edge of the clock. SBO0
Figure 5-2-6 Synchronous Serial Transmit/Receive Timing (data is received at the falling edge and transmitted at the rising edge)
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5-3 Half-duplex UART Serial Interface
5-3-1 Overview
Setup and operation of UART transmission and reception are described below.
5-3-2 Setup and Operation
s Transmission (1) (2)
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(3) (4) (5) (6)
Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0). Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. Select the clock source with the SC0CK1 to 0 flags of serial interface 0 mode register 1 (SC0MD1). Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock source frequency by 8. Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to enable or disable parity.
When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are toggled, the transfer bit count may change.
The TXD pin goes to a high level after transmission is complete.
Setting the SC0FM flag of the SC0MD2 register to frame mode automatically sets the SC0LNG2 to 0 flags of the SC0MD0 register.
After the transfer is complete, the SC0LNG2 to 0 flags of the SC0MD0 register are automatically set with the transfer bit count.
Set the SC0CKM flag of the SC0MD1 register to "1" to divide the clock source frequency by 8.
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(7) (8) (9)
Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set.
(10) (11) (12) (13) (14) (15) (16)
If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the SC0PM1~0 flags of the SC0MD2 register to specify the added parity bit. Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame mode. Set the SC0BRKE flag of the SC0MD2 register to control break status transmission. Select the SC0SBOM flag of the SC0MD3 register. Select the SC0IOM flag of the SC0MD3 register. Set bit 0 of the port 0 direction control register (P0DIR) to the output mode. Select serial communication by setting the SC0SBOS flag of the SC0MD3 register to "1." Set transmit data to serial interface 0 transmit/receive shift register (SC0TRB). This will start the serial transmission. When the serial transmission begins, the SC0BSY flag of the SC0CTR register is set to "1," indicating that a serial transfer is in progress. When the serial transmission is complete, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "0."
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TXD
Parity enabled
Parity bit
Stop bit
Stop bit
TXD
Parity disabled
Stop bit
Stop bit
Interrupt Parity enabled
Interrupt Parity disabled
SC0BSY Parity enabled
SC0BSY Parity disabled
Figure 5-3-1 UART Transmission Timing
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s Reception (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0). Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. Select the clock source with the SC0CK1~0 flags of serial interface 0 mode register 1 (SC0MD1). Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock source frequency by 8. Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to enable or disable parity. If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the SC0PM1 to 0 flags of the SC0MD2 register to specify the added parity bit. Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame mode. Select the SC0IOM flag of the SC0MD3 register. When the SC0IOM flag of the SC0MD3 register is specified that the pin is independent, set bit 1 of the port 0 direction control register (P0DIR) to the input mode. Set bit 0 of the port 0 pull-up resistor control register (P0PLU). Select serial communication by setting the SC0SBIS flag of the SC0MD3 register to "1." When the serial transmission begins, the SC0BSY flag of the SC0CTR register is set to "1," indicating that a serial transfer is in progress. When the serial transmission is complete, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "1."
When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are toggled, the transfer bit count may change. The TXD pin goes to a high level after reception is complete.
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(11) (12) (13) (14)
Serial interface 0 begins operation when the SC0SBOS or SC0SBIS flag is set to "1." Set the SC0SBOS or SC0SBIS flag after all conditions have been set.
Setting the SC0FM flag of the SC0MD2 register to frame mode automatically sets the SC0LNG2 to 0 flags of the SC0MD0 register.
One machine cycle after the stop bit has been received, the start condition will no longer be accepted. Therefore, consecutive reception must be performed carefully.
After the transfer is complete, the SC0LNG2 to 0 flags of the SC0MD0 register are automatically set with the transfer bit count.
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RXD
Parity enabled
Parity bit
Stop bit
Stop bit
RXD
Parity disabled
Stop bit
Stop bit
Interrupt Parity enabled
Interrupt Parity disabled
SC0BSY Parity enabled
SC0BSY Parity disabled
Figure 5-3-2 UART Reception Timing
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Half-duplex UART Serial Interface
Chapter 5 Serial Functions
5-3-3 How to Use the Baud Rate Timer
Refer to the following when using the baud rate timer to set the UART transfer speed. (1) Specifying the timer clock source The clock source is specified by the TM3CKS3 to 1 flags of the timer 3 mode register (TM3MD). (2) Setting the compare register The compare register value is set in the timer 3 compare register (TM3OC). This set value is computed according to the following formula: overflow period = (compare register set value + 1) x timer clock period baud rate = 1/(overflow period x 2 x 8) SC0MD1(SC0CKM) compare register set value = timer clock frequency/(baud rate x 2 x 8) - 1 Table 5-3-1 UART Transfer Rate
Transfer Speed (bps) fosc (MHz) 4.0
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300
-- 104 -- -- 109 -- -- 208 -- -- 218 -- -- -- 78 -- -- 104 -- -- 109 -- -- 130 -- 300 -- -- 300 -- -- 300 -- -- 300 -- -- -- 300 -- -- 300 -- -- 300 -- -- 300
1200
208 -- -- 218 -- -- -- 52 -- -- 55 -- -- 78 -- -- 104 -- -- 109 -- -- 130 -- 1202 -- -- 1201 -- -- -- 1201 -- -- 1190 -- -- 1202 -- -- 1202 -- -- 1201 -- -- 1202 --
2400
Set Calculated Value Value
4800
Set Calculated Value Value
9600
19200
13 -- -- -- -- -- 26 -- -- 27 -- -- 39 -- -- 52 -- -- 55 -- -- 65 -- -- 19230 -- -- -- -- -- 19230 -- -- 19398 -- -- 19230 -- -- 19230 -- -- 19045 -- -- 19231 -- --
Set Calculated Set Calculated Value Value Value Value
Set Calculated Set Calculated Value Value Value Value
Set the values from this table (minus 1) in the compare register.
4.19
8.0
8.38
12.0
16.0
16.76
20.0
fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16
104 -- -- 109 -- -- 208 -- -- 218 -- -- -- 39 -- -- 52 -- -- 55 -- -- 65 --
2403 -- -- 2402 -- -- 2404 -- -- 2403 -- -- -- 2403 -- -- 2404 -- -- 2381 -- -- 2404 --
52 -- -- 55 -- -- 104 -- -- 109 -- -- 156 -- -- 208 -- -- 218 -- -- -- 33 --
4807 26 9615 -- -- -- -- -- -- 4761 27 9699 -- -- -- -- -- -- 4807 52 9615 -- -- -- -- -- -- 4805 55 9523 -- -- -- -- -- -- 4808 78 9615 -- -- -- -- -- -- 4808 104 9615 -- -- -- -- -- -- 4805 109 9610 -- -- -- -- -- -- 130 9615 -- -- 4735 -- -- -- --
Example: The timer 3 clock source is fs/4 (fosc = 8MHz) and a baud rate of 300 bps is desired. Since fs=fosc/2, compare register set value = (8 x 106/2/4)/(300 x 2 x 8) - 1 =207 = X'CF'
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Chapter 5 Serial Functions
5-4 Serial Interface Control Registers
5-4-1 Overview
7 registers control the serial interface. See table 5-4-1.
Table 5-4-1 Serial Interface Registers
Name SC0MD0 SC0MD1 SC0MD2 SC0MD3 SC0CTR SC0TRB SC0RXB
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Address X'03F50' X'03F51' X'03F52' X'03F53' X'03F54' X'03F55' X'03F56'
R/W R/W R/W R/W R/W R/W W R
Function Serial interface 0 mode register 0 Serial interface 0 mode register 1 Serial interface 0 mode register 2 Serial interface 0 mode register 3 Serial interface 0 control register Serial interface 0 transmit/receive shift register Serial interface 0 receive data buffer
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Serial Interface Control Registers
Chapter 5 Serial Functions
5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer
(1) Serial interface 0 transmit/receive shift register (SC0TRB) This 8-bit, writable register shifts the transmission data and the reception data. The direction of transfer can be specified as LSB first or MSB first.
7 SC0TRB 6 5 4 3 2 1 0
SC0TRB7 SC0TRB6 SC0TRB5 SC0TRB4 SC0TRB3 SC0TRB2 SC0TRB1 SC0TRB0 (at reset: undefined)
Figure 5-4-1 Serial Interface 0 Transmit/Receive Shift Register (SC0TRB: X'03F55', W) (2) Serial interface 0 receive data buffer (SC0RXB)
7 SC0RXB 6 5 4 3 2 1 0
SC0RXB7 SC0RXB6 SC0RXB5 SC0RXB4 SC0RXB3 SC0RXB2 SC0RXB1 SC0RXB0 (at reset: undefined)
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Figure 5-4-2 Serial Interface 0 Receive Data Buffer (SC0RXB: X'03F56', R)
Serial Interface Control Registers
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Chapter 5 Serial Functions
5-4-3 Serial Interface Mode Registers
(1) Serial interface 0 mode register (SC0MD0)
7 SC0MD0 - 6 5 4 3 2 1 0 (at reset: -00XX000)
SC0CE0 SC0CE1 SC0DIR SC0STE SC0LNG2 SC0LNG1 SC0LNG0
SC0LNG2 SC0LNG1 SC0LNG0 Transfer bit count 0 0 1 0 1 1 0 1 0 1 0 1 0 1 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit
SC0STE 0 1
Selection of synchronous serial start condition Disable start condition Enable start condition
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SC0DIR 0 1
First bit to be transferred MSB first LSB first Receive data Transmit data input edge output edge Rising Falling Falling Rising Falling Rising Falling Rising
SC0CE0 SC0CE1 0 0 1 1 0 1 0 1
Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W)
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Serial Interface Control Registers
Chapter 5 Serial Functions
(2) Serial interface 0 mode register 1 (SC0MD1)
7 SC0MD1 - 6 - 5 4 3 2 1 0 (at reset: --X00000) Transmit/receive interrupt request flag Transmit interrupt request Receive interrupt request
SC0CKM SC0CK1 SC0CK0 SC0BRKF SC0ERE SC0TRI
SC0TRI 0 1
SC0ERE 0 1
Error monitor No error Error Break status receive monitor Data Break
SC0BRKF 0 1
SC0CK1 0 0
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SC0CK0 0 1 0 1
Clock source fs/2 fs/4 fs/16 BC3x1/2(1/2 of timer 3 overflow)
1 1
SC0CKM 0 1
Divide clock frequency by 8 Do not divide by 8 Divide by 8
An external clock can be selected as the clock source by setting the SBT0 pin to the input mode.
Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W)
Serial Interface Control Registers
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Chapter 5 Serial Functions
(3) Serial interface 0 mode register 2 (SC0MD2)
7 SC0MD2 - 6 - 5 4 3 2 1 0 (at reset: --000XXX)
SC0BRKE SC0FM1 SC0FM0 SC0PM1 SC0PM0 SC0NPE
SC0NPE 0 1
Parity enable Parity enabled Parity disabled
SC0PM1 SC0PM0 0 1 0 1
Added bit specification Transmission Reception Check for 0 Check for 1
Check for odd parity Check for even parity
0 1
Normally add 0 Normally add 1 Add odd parity Add even parity
SC0FM1 SC0FM0 0
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Frame mode specification 7 data bits + 1 stop bit 7 data bits + 2 stop bits 8 data bits + 1 stop bits 8 data bits + 2 stop bits
0 1 0 1
1
SC0BRKE 0 1
Break status transmit control Data Break
Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W)
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Chapter 5 Serial Functions
(4) Serial interface 0 mode register 3 (SC0MD3)
7 SC0MD3 -
6 -
5
4
3
2
1
0 (at reset: --000000)
SC0IOM SC0SBOM SC0SBTM SC0SBOS SC0SBIS SC0SBTS
SC0SBTS 0 1
SBT0 pin function selection Port Serial clock pin
SC0SBIS 0 1
SBI0 input control "1" input Serial input
SC0SBOS 0 1
SBO0 pin function selection Port Serial communication
SC0SBTM 0 1
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SBT0 pin configuration selection Push-pull output N-channel open-drain output
SC0SBOM 0 1
SBO0 pin configuration selection Push-pull output N-channel open-drain output
SC0IOM 0 1
SBI0/SBO0 pin connection Unconnected Connected
Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W)
Serial Interface Control Registers
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Chapter 5 Serial Functions
5-4-4 Serial Interface Control Register
(1) Serial interface 0 control register (SC0CTR)
7 SC0CTR 6 5 - 4 - 3 2 1 0 - (at reset: 00XX000X)
SC0BSY SC0CMD
SC0FEF SC0PEK SC0ORE
SC0ORE 0 1
Overrun error detection No Error Error
SC0PEK 0 1
Parity error detection No Error Error
SC0FEF 0 1
Framing error detection No Error Error Synchronous serial/ UART selection Synchronous serial UART
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SC0CMD 0 1
SC0BSY 0 1
Serial bus status Other use Serial transmission in progress
Figure 5-4-7 Serial Interface 0 Control Register (SC0CTR: X'03F54', R) (R/W available with SC0CMD only)
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Serial Interface Control Registers
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Chapter 6
A/D Conversion Functions
6
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Chapter 6 A/D Conversion Functions
6-1 Overview
The MN101C117 has an internal A/D converter with 10-bit resolution. A sample-and-hold circuit is contained on-chip and software can switch the analog input between channels 0 to 7 (AN0 to AN7). When the A/D converter is stopped, power consumption can be reduced by turning off the internal ladder resistors.
ANCTR1
- - - - - - - ANST
0
ANBUF1
ANBUF10 ANBUF11 ANBUF12 ANBUF13 ANBUF14 ANBUF15 ANBUF16 ANBUF17
0
ANBUF0
- - - - - - ANBUF06 ANBUF07
0
ANCTR0
ANCHS0 ANCHS1 ANCHS2 ANLADE ANCK0 ANCK1 ANSH0 ANSH1
0
7
A/D conversion control
7
7
7
3
VDD
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AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VSS
2 MUX Sample & hold
2 10-bit A/D comparator
Upper 8 bits of A/D conversion data Lower 2 bits of A/D conversion data
fs/2 fs/4 fs/8 fx x 2
MUX
1/2 1/6 1/18 MUX
Figure 6-1-1 A/D Converter Block Diagram
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Overview
Chapter 6 A/D Conversion Functions
6-2 A/D Conversion
The procedures for operating the A/D conversion circuit are listed below. (1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one of pins AN7 to AN0 (PA7 to PA0) as the analog input. (2) Set the ANCK1 and ANCK0 flags of A/D control register 0 to select the A/D conversion clock. Make this setting such that the period of the conversion clock (TAD), which is based on the oscillator, is greater than 800ns. (3) With the ANSH1 and ANSH0 flags of A/D control register 0, set the sample-and-hold time. Select a value for the sample and hold time that is suitable for the analog input impedance. (4) Set the ANLADE flag of A/D control register 0 to "1" so that current flows through the ladder resistors and the A/D converter is on standby. Note: Steps 1 to 4 above may performed all at the same time. (5) Set the ANST flag of A/D control register 1 (ANCTR1) to "1" to start the A/D conversion. (6) After the sample-and-hold time set in step 3, the sampled A/D conversion data is sequentially compared to determine its value beginning with the MSB. (7) When the A/D conversion is complete, the ANST bit is cleared to "0" and conversion results are stored in A/D buffers (ANBUF0, 1). At the same time, an A/D complete interrupt request (ADIRQ) is generated.
TAD 1~2 3 4 12
Start the A/D conversion after the current flowing through the ladder resistors stabilizes. The time constant calculated time from the ladder resistance (max. 80 k) and the external bypass capacitor connected between Vdd and Vss should be used as the criteria for the wait time.
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ANST A/D conversion start TS
Sampling Hold Bit 9 Bit 8 comparison comparison Bit 0 comparison
A/D conversion complete
Determine bit 9 value
Determine bit 8 value
Determine Determine bit 1 value bit 0 value
A/D interrupt
Figure 6-2-1 A/D Conversion Timing
A/D Conversion
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Chapter 6 A/D Conversion Functions
The following items must be implemented to maintain the accuracy of the A/D converter: 1. Use a maximum input pin impedance, R, of 500k1 with an external capacitor, C, that is minimum 1,000pF and maximum 1F1. 2. Take the RC time into consideration when setting the A/D conversion interval. 3. Changing the output level of the microcomputer or switching peripheral circuitry on or off when the A/D converter is in use may cause the analog input pin or current pin to fluctuate resulting in a loss of precision. During setup and evaluation, verify the waveform of the analog input pin.
Equivalent circuit of analog signal output R A/D input pin
Microcomputer
C
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1 FC1000pF where R500k
1
Vss
1 These values are reference values.
Figure 6-2-2 Recommended Circuit When Using A/D Conversion
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A/D Converter Control Registers
Chapter 6 A/D Conversion Functions
6-3 A/D Converter Control Registers
6-3-1 Overview
Four registers control the A/D converter. See table 6-3-1.
Table 6-3-1 A/D Converter Control Registers
Name ANCTR0 ANCTR1 ANBUF0 ANBUF1 Address X'03F90' X'03F91' X'03F92' X'03F93' R/W R/W R/W R R Function A/D control register 0 A/D control register 1 A/D buffer 0 A/D buffer 1
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A/D Converter Control Registers
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Chapter 6 A/D Conversion Functions
6-3-2 A/D Control Register (ANCTR)
This readable and writable 8-bit register controls the operation of the A/D converter.
7 ANCTR0 6 5 4 3 2 1 0 (at reset: XXXX0XXX)
ANSH1 ANSH0 ANCK1 ANCK0 ANLADE ANCHS2 ANCHS1 ANCHS0
ANCHS2 ANCHS1 ANCHS0 Analog input selection 0 0 1 0 1 1 0 1 0 1 0 1 0 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
ANLADE 0
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A/D ladder resistor control A/D ladder resistors off A/D ladder resistors on
1
ANCK1 0 1
ANCK0 0 1 0 1 fs/2 fs/4 fs/8
A/D conversion clock selection1
Use prohibited
ANSH1 0 1
ANSH0 0 1 0 1
Sample and hold time setting2 TAD x 2 TAD x 6 TAD x 18 Use prohibited
(1) A/D control register 0 (ANCTR0)
1:Specify that where the period of the A/D conversion clock is greater than 800ns. 2:Sample-and-hold time is determined by the analog input impedance. TAD indicates the period of the A/D conversion clock.
Figure 6-3-1 A/D Control Register 0 (ANCTR0: X'03F90', R/W)
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Chapter 6 A/D Conversion Functions
(2) A/D conversion control register 1 (ANCTR1)
7 ANCTR1 ANST 6 5 4 3 2 1 0 (at reset: 0-------)
ANST 0 1
A/D conversion status
A/D conversion completed or stopped A/D conversion started or in progress
Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W)
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A/D Converter Control Registers
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Chapter 6 A/D Conversion Functions
6-3-3 A/D Buffers (ANBUF)
These read-only registers store the A/D conversion results. (1) A/D buffer 0 (ANBUF0) This register stores the lower 2 bits of the A/D conversion results.
7
ANBUF0
6
5
4
3
2
1
0
(at reset: XX------)
ANBUF07 ANBUF06
Figure 6-3-3 A/D Buffer 0 (ANBUF0: X'03F92', R)
(2) A/D buffer 1 (ANBUF1) This register stores the upper 8 bits of the A/D conversion results.
7
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6
5
4
3
2
1
0
(at reset: XXXXXXXX)
ANBUF1
ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10
Figure 6-3-4 A/D Buffer 1 (ANBUF1: X'03F93', R)
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A/D Converter Control Registers
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Chapter 7
AC Zero-Cross Circuit/Noise Filter
7
121
Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-1 Overview
The P21/SENS pin is the input pin for the AC zero-cross detection circuit. The AC zero-cross detection circuit outputs a high level when the input is at an intermediate level, and a low level at all other times.
FLOAT1
P7RDWN PARDWN P21IM - - - - -
0
7
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P21/IRQ1/SENS
AC zero-cross detection circuit
MUX
P21 input/IRQ1 to noise filter (See figure 7-3-1.)
Figure 7-1-1 P21 Input Circuit Block Diagram
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Overview
Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-2 AC Zero-Cross Circuit Operation
7-2-1 Setup and Operation
Settings for zero-cross circuit operation are listed below. (1) (2) (3) (4) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1. Set the NF1EN and NF1CK1 to 0 flags of the NFCTR register to set the noise filter and its sampling clock. With the P21IM flag of the FLOAT1 register, set the P21 pin to zero-cross detection. An IRQ1 interrupt is generated by the falling edge or the rising edge of AC zero-cross detection output.
AC line waveform VDD
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10 ms at 50Hz 8.3 ms at 60Hz
VSS Ideal IRQ1 Actual IRQ1 Point A
Figure 7-2-1 AC Line Waveform and IRQ Generation Timing
Actual IRQ interrupt requests will be generated multiple times. Therefore, the software must filter this signal before making any evaluations. When noise filtering is selected for use, the amount of evaluation processing by the software will be reduced. However, if the OSC stops, a return from the backup mode will not be possible.
AC Zero-Cross Circuit Operation
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-3 Noise Filter
7-3-1 Overview
External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit. This circuitry can be used for remote control signal reception.
Data bus
NFCTR
IRQ0: External interrupt 0 IRQ1: External interrupt 1
fs/22 fs/28 fs/29 fs/210
P20/IRQ0
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2 2
NF0EN NF0CKS0 NF0CKS1 NF1EN NF1CKS0 NF1CKS1
0
7
MUX
Noise filter MUX To IRQ0 interrupt
fs/22 fs/28 fs/29 fs/2
P21/IRQ1/SENS AC zero-cross circuit (Fig.7-1-1)
10
MUX
Noise filter MUX To IRQ1 interrupt
Figure 7-3-1 Noise Filtering Circuit Block Diagram
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Noise Filter
Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-3-2 Example Input and Output Waveforms for Noise Filter
When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register (NFCTR). The waveform input to the IRQ1 pin is also sampled based on the clock specified by the NF1CKS0 and NF1CKS1 flags. If the sampled level remains the same for 3 consecutive samples, it is sent the CPU; otherwise, the previous level is maintained.
Noise filtering cannot be used in the STOP or HALT modes.
Sampling
Input
0 Waveform after noise filtering
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0
1
1
1
1
1
0
0
Figure 7-3-2 Noise Filter Input and Output Waveform Example
Noise Filter
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-4 AC Zero-Cross Control Register
7-4-1 Overview
Four registers control the AC zero-cross circuit.
Table 7-4-1 AC Zero-Cross Control Register
[ 2-4-3 "Interrupt Control Registers s External Interrupt Control Registers"]
Name IRQOICR IRQ1ICR
Address X'03FE2' X'03FE3' X'03F4B' X'03F8A'
R/W R/W R/W R/W R/W
Function External interrupt control register 0 External interrupt control register 1 Pin control register 1 Noise filter control register
[ 3-2-2 "I/O Port Control Registers s Pin Control Registers"]
FLOAT1 NFCTR
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AC Zero-Cross Control Register
Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-4-2 Noise Filter Control Register (NFCTR)
This 6-bit readable and writable register controls the noise filter.
7 NFCTR - 6 - 5 4 3 2 1 0 (at reset: --000000)
NF1CKS1 NF1CKS0 NF1EN
NF0CKS1 NF0CKS0 NF0EN
NF0EN 0 1
IRQ0 noise filter setup and operation IRQ0 noise filter off IRQ0 noise filter on
NF0CKS1 NF0CKS0 0 1 0 1 0 1
IRQ0 noise filter sampling period selection fs/2 fs/28 fs/2 fs/2
9 10 2
NF1EN
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IRQ1 noise filter setup and operation IRQ1 noise filter off IRQ1 noise filter on
0 1
NF1CKS1 NF1CKS0 0 1 0 1 0 1
IRQ1 noise filter sampling period selection fs/2 fs/28 fs/2 fs/2
9 10 2
Figure 7-4-1 Noise Filter Control Register (NFCTR: X'03F8A', R/W)
AC Zero-Cross Control Register
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
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128
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Appendices
8
129
Chapter 8 Appendices
8-1 EPROM Versions
8-1-1 Overview
EPROM version is microcomputer which was replaced with the mask ROM of the MN101C11 with an electronically programmable 16-KB EPROM. Because the MN101CP117**(**=DP,BF,HP) is sealed in plastic, once data is written to the internal PROM it cannot be erased. Because the PX-AP101C11-SDC and PX-AP101C11-FBC are sealed in a ceramic package that has a window, written data can beerased by illumination with ultraviolet light. Plastic package uses a 42-pin shrink DIL package, 44-pin flat package, and 48-pin flat package. Ceramic packages uses a 42-pin shrink DIL package and 44-pin flat package. Setting the EPROM version to EPROM mode, halts microcomputer functions, and the internal EPROM can be programmed. Refer to the EPROM mode pin diagram in figure 9-4-3 to 5.
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The specification for writing to the internal EPROM are the same as for a general-purpose 256Kbit EPROM(Vpp=12.5V, tpw=0.2ms). Therefore, by replacing theEPROM Version's 42-pin socket with a special 28-pin socket adapter(supplied by Panasonic) having the same configuration as a normal EPROM, a general-purpose EPROM writer can be used to perform read and write operations. The EPROM Version is described on the following items: - Cautions on use of the internal EPROM - Erasing written Data in Windowed Package(PX-AP101C11-SDC, PXAP101C11-FBC) - Characteristics of EPROM Versions - Writing to the Microcomputer with Internal EPROM - Cautions on operating a ROM writer - Option bit - Connections of a writing adaptor.
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Chapter 8 Appendices
8-1-2 Cautions on Use
EPROM Versions differs from the MN101C11* in some of its electrical characteristics. The user should be aware of these differences. (1) To prevent data from being erased by ultraviolet light after a program is written, affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU. (PX-AP101C11-SDC, PX-AP101C11-FBC) (2) Due to device characteristics of the MN101CP11XXX, a writing test cannot be performed on all bits. Therefore, storage of the written data cannot be guaranteed in some cases. (3) When a program is written, verify that Vc power supply(6V) is connected before applying the Vpp power supply(12.5V). Disconnect the Vpp supply before disconnecting the Vcc supply. (4) Vpp should never exceed 13.5V including overshoot.
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(5) If a device is removed while a Vpp of +12.5V is applied, device reliability may be damaged. (6) At CE=VIL, do not change Vpp from VIL to +12.5V or from +12.5V to VIL. (7) From the time after a program is written until just before mounting, storage at a high temperature is recommended. Program/Read
High temperature storage 125C - 48H
Read
Mounting
EPROM Versions
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Chapter 8 Appendices
8-1-3 Erasing Written Data in Windowed Packages (PX-AP101C11-SDC, PX-AP101C11-FBC)
In an internal EPROM with windowed packaging, data is erased("0" "1") when UV light at 253.7nm permeates the window to irradiate the chip. The recommended exposure is 10W * s/cm2. This coverage can be achieved by using a commercial UV lamp positioned 2 to 3cm above the package for 15-20 minutes(when the illumination intensity of the package surface is12000W/cm2). Remove any filters attached to the lamp. By installing a mirrored reflector plate in the lamp, illumination intensity will increase by afactor of 1.4 to 1.8, decreasing the erasure time. If the window becomes dirty with oil, adhesive, etc., UV light permeability will decrease, causing the erasure time to increase considerably. If this happens, clean with alcohol or another solvent that will not harm the package. The recommended above provides sufficient leeway, with several times the amount of time it takes to erase all the bits. However, this value will reliably erase data over all temperature and voltage ranges, and should not be altered. The level of illumination should be regularly checked and the lamp operation verified.
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Erasure begins when EPROM is exposed to light with a wavelength shorter than 400nm. Since fluorescent light and sunlight have wavelengths in this range, exposure to these light sources for extended periods of time could cause inadvertant erasure. To prevent this, cover the window with an opaque label. Data is not erased at wavelengths longer than 400 to 500nm. However, because of typical semiconductor characteristics, the circuit may malfunction if the chip is exposed to an extremely high illumination intensity. The chip will operate normally if this exposure is stopped. However, for areas where it is continuous, take necessary precautions.
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Chapter 8 Appendices
8-1-4 Characteristics of EPROM Version
The MN101C11*(mask ROM version) and the Microcomputer with internal EPROM version have the following differences. Table 8-1-1 Difference between MN101C*(Mask ROM version) and Internal EPROM version)
Operating temperature
MN101C11 -40 to 85
ROM ver.
Internal EPROM version -20 to 85 4.5 to 5.5V 0.1 s/20MHz 2.7 to 5.5v 0.25 s/8MHz 2.7 to 5.5v 1.00 s/2MHz
Operating voltage
4.5 to 5.5V 0.1 s/20MHz 2.7 to 5.5v 0.25 s/8MHz 2.0 to 5.5v 1.00 s/2MHz
Pin DC characteristics Hi-speed,low-speed oscillation start control,runaway detection period settup Package selection
Output current,input current and input judge level are the same. ROM option Internal ROM final address data be used as option data. (Final address =X'07FFF) EPROM option EPROM final address data be used as option data. (Final address=X'07FFF)
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There are no other functional differences.
EPROM Versions
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Chapter 8 Appendices
8-1-5 Writing to Microcomputer with Internal EPROM
s Fit in the writing adapter and position the No.1 pin.
No.1 pin must be matched to this position.
*The socket of an adapter varies according to the package types.
Package type 42-SDIP 44-QFP 48-QFH
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Product name OTP42SD-101CP11 OTP44QF14-101CP11 OTP48FH7-101CP11
No.1 Pin
No.1 Pin
No.1 Pin
(MN101CP117DP)
(MN101CP117BF)
(MN101CP117HP)
(top view)
(PX-AP101C11-SDC)
(top view)
(PX-AP101C11-FBC) (side view)
Figure 8-1-1 Mount on the writing adapter and position of No.1 pin.
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s ROM writer Selection The device names should be set up as listed below.
Table 8-1-2 Device selection
Equip. name Pecker 30 1890A Lab Site
Vendor Avarl Data Minato Electronics Data I/O
Device name Hitachi 27C256 Hitachi 27C256 Hitachi 27C256
Remarks
Do not run ID check and pin connection inspection.
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The above settings are based on the standard samples. When you use the other equipment than the ones listed, contact the nearest semiconductor design center.(Refer to the sales office table attached at the end of the manual.)
EPROM Versions
135
Chapter 8 Appendices
8-1-6 Cautions on Operating the ROM Writer
s Cautions on operating the ROM writer (1)The Vpp programming voltage for the EPROM versions is 12.5V. Programming with a 21-volt ROM writer can lead to damage. The ROM writer specifications must match those for standard 1-megabit EPROMS:Vpp=12.5V V;tpw=0.2ms. (2)Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter. Faulty connections can lead to damage. (3)After clearing all memory of the ROM writer, load the program. (Write the data X'FF' on the address X'0000' to X'7FFF'.) (4)After confirming the device name, write the addresses from the start to the final address. (5)The option bits for supporting the mask option are prepared at the final ROM address. This writer has no internal ID codes of Silicon Signature and Intelligent Identifier of the auto-device selection command of ROM writer. If the auto-device selection command is to be executed for this writer, the device is likely damaged. Therefore, never use this command.
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s When disabling the writing When disabling the writing, check the following points. (1)Check that the device is mounted correctly on the socket.(pin bending, connecting failure). (2)Check that the erase check result is no problem. (3)Check that the adapter type is identical to the device name. (4)Check that the writing mode is set correctly. (5)Check that the data is correctly transferred to the ROM writer. (6)Recheck the check points (1),(2) and (3) provided on the above paragraph of iCautions on Handling the ROM writeri. When the writing is disabled even after the above check points are confirmed and the device is replaced with another one, contact the nearest semiconductor design center. (See the attached sales office table.)
136
EPROM Versions
Chapter 8 Appendices
8-1-7 Option Bit
The MN101C117 and the MN101CP117 control the oscillation mode after resetting as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address (X'7FFF) of the built-in ROM. s Option bit
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Fig. 8-1-2 Option bit(Address: X'07FFF')
EPROM Versions
137
Chapter 8 Appendices
8-1-8 Writing Adapter Connection
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Package Code SDIP042-P-0600 Fig. 8-1-3 MN1-1CP117-DP(DC)EPROM Writing Adapter Connections
Refer to the pin connection drawing of the 256-bit EPROM(27C256).
138
EPROM Versions
Chapter 8 Appendices
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Package code: QFP044-P-1010 Pin pitch: 0.8mm
Fig. 8-1-4 MN101CP117-BL(BC)EPROM Writing Adapter Connections
Refer to the pin connection drawing of the 256-bit EPROM(27C256).
EPROM Versions
139
Chapter 8 Appendices
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Package code: QFH048-P-0707 Pin pitch: 0.5mm
Fig. 8-1-5 MN101CP117-HP EPROM Writing Adapter connections
Refer to the pin connection drawing of the 256-bit EPROM(27C256).
140
EPROM Versions
Chapter 10 Appendices
8-2 Instruction Set
MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag Code Cycle Repeat Expand 1 VF NF CF ZF Size Machine Code Notes Page
2
3
4
5
6
7
8
9
10
11
25
Data move instructions MOV MOV Dn,Dm MOV imm8,Dm MOV Dn,PSW MOV PSW,Dm MOV (An),Dm MOV (d8,An),Dm MOV (d16,An),Dm MOV (d4,SP),Dm MOV (d8,SP),Dm MOV (d16,SP),Dm MOV (io8),Dm MOV (abs8),Dm MOV (abs12),Dm MOV (abs16),Dm MOV Dn,(Am) MOV Dn,(d8,Am) MOV Dn,(d16,Am) MOV Dn,(d4,SP) MOV Dn,(d8,SP) MOV Dn,(d16,SP) MOV Dn,(io8) MOV Dn,(abs8) MOV Dn,(abs12) MOV Dn,(abs16) MOV imm8,(io8) MOV imm8,(abs8)
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DnDm imm8Dm DnPSW PSWDm mem8(An)Dm mem8(d8+An)Dm mem8(d16+An)Dm mem8(d4+SP)Dm mem8(d8+SP)Dm mem8(d16+SP)Dm mem8(IOTOP+io8)Dm mem8(abs8)Dm mem8(abs12)Dm mem8(abs16)Dm Dnmem8(Am) Dnmem8(d8+Am) Dnmem8(d16+Am) Dnmem8(d4+SP) Dnmem8(d8+SP) Dnmem8(d16+SP) Dnmem8(IOTOP+io8) Dnmem8(abs8) Dnmem8(abs12) Dnmem8(abs16) imm8mem8(IOTOP+io8) imm8mem8(abs8) imm8mem8(abs12) imm8mem8(abs16) Dnmem8(HA) mem16(An)DWm mem16(An)Am mem16(d4+SP)DWm mem16(d4+SP)Am mem16(d8+SP)DWm mem16(d8+SP)Am mem16(d16+SP)DWm mem16(d16+SP)Am mem16(abs8)DWm mem16(abs8)Am mem16(abs16)DWm mem16(abs16)Am DWnmem16(Am) Anmem16(Am) DWnmem16(d4+SP) Anmem16(d4+SP) DWnmem16(d8+SP) Anmem16(d8+SP) DWnmem16(d16+SP) Anmem16(d16+SP) DWnmem16(abs8) Anmem16(abs8) DWnmem16(abs16) Anmem16(abs16) DWnmem16(HA) Anmem16(HA) sign(imm8)DWm zero(imm8)Am imm16DWm
- -
- -
- -
- -
2 4 3
1 2 3 2 2 2 4 2 3 4 2 2 2 4 2 2 4 2 3 4 2 2 2 4 3 3 3 5 2 3 4 3 3 4 4 5 5 3 3 5 5 3 4 3 3 4 4 5 5 3 3 5 5 3 3 2 2 3
1010 DnDm 1010 DmDm <#8. 0010 1001 01Dn 0010 0001 01Dm 0100 1ADm 0110 1ADm 0010 0110 01Dm .... ...> ...> .... ...>
1
...>
25 26 26 27 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 2 4 7 3 5 7 4 4 5 7 2 4 7 3 5 7 4 4 5 7 6 6 7 9 2 2 3 3 3 5 5 7 7 4 4 7 7 2 3 3 3 5 5 7 7 4 4 7 7 2 2 4 4 6
...> .... .... ...>
27 28
2 3
28 29 29 30 30 31 31 32
....
...>
0100 01Dm 0100 00Dm 0010 0111 01Dn .... ...> ...> .... <#8. ...> .... ...> ...> ...> <#8. ...> ...> <#8. ...> .... ...> ...> .... .... ...>
2 3
32 33 33 34 34 35 35 36 36 37 37 38 38 39 40
0101 01Dn 0101 00Dn
0001 0100 <#8. 0001 0101 1110 010a 0010 1110 011d ...> .... .... .... ....
MOV imm8,(abs12) MOV imm8,(abs16) MOV Dn,(HA) MOVW MOVW (An),DWm MOVW (An),Am MOVW (d4,SP),DWm MOVW (d4,SP),Am MOVW (d8,SP),DWm MOVW (d8,SP),Am MOVW (d16,SP),DWm MOVW (d16,SP),Am MOVW (abs8),DWm MOVW (abs8),Am MOVW (abs16),DWm MOVW (abs16),Am MOVW DWn,(Am) MOVW An,(Am) MOVW DWn,(d4,SP) MOVW An,(d4,SP) MOVW DWn,(d8,SP) MOVW An,(d8,SP) MOVW DWn,(d16,SP) MOVW An,(d16,SP) MOVW DWn,(abs8) MOVW An,(abs8) MOVW DWn,(abs16) MOVW An,(abs16) MOVW DWn,(HA) MOVW An,(HA) MOVW imm8,DWm MOVW imm8,Am MOVW imm16,DWm
4 2 2 3 3
40 41 41 42 42 43 43 44 44
...> ...>
1100 011d 1100 010a 0010 1100 011d 1111 010A 0010 1111 011D ...> .... .... .... .... ...> ...>
4 2 2 3 3
.... ....
...> ...>
45 45 46 46 47 47 48 48 49 49 50 50
1101 011D 1101 010A 0010 1101 011D ...> .... .... ...>
5 6
.... ....
...> ...>
51 51 52 52 53 53 54
Note: "Page" refers to the corresponding page in the Instruction Manual.
1 d8 sign extended 2 d4 zero extended 3 d8 zero extended
4 A=An, a=Am 5 #8 sign extended 6 #8 zero extended
Instruction Set
141
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MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code Notes Page
2
3
4
5
6
7
8
9
10
11
54 55 55 1 56 56 57 2 57 58 58 59 59 3 60
MOVW imm16,Am MOVW SP,Am MOVW An,SP MOVW DWn,DWm MOVW DWn,Am MOVW An,DWm MOVW An,Am PUSH PUSH Dn PUSH An POP POP Dn POP An EXT EXT Dn,DWm
imm16Am SPAm AnSP DWnDWm DWnAm AnDWm AnAm SP-1SP,Dnmem8(SP) SP-2SP,Anmem16(SP) mem8(SP)Dn,SP+1SP mem16(SP)An,SP+2SP sign(Dn)DWm
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
6 3 3 3 3 3 3 2 2 2 2 3
3 3 3 3 3 3 3 3 5 3 4 3
1101 111a <#16 0010 0000 100a 0010 0000 101A 0010 1000 00Dd 0010 0100 11Da 0010 1100 11Ad 0010 0000 00Aa 1111 10Dn 0001 011A 1110 10Dn 0000 011A 0010 1001 000d 0011 0011 DnDm 1000 00Dm <#4> 0000 10Dm <#8. 0011 1011 DnDm 0010 0101 00Dd 0010 0101 10Da 1110 110a <#4> 0010 1110 110a <#8. 0010 0101 011a <#16 1111 1101 <#4> 1111 1100 <#8. 0010 1111 1100 <#16 0010 0101 010d <#16 0010 1000 1aDn 0010 1001 1aDn 0010 1010 DnDm 1000 01Dn 0010 1010 DmDm <#8. 0010 1011 DnDm 0010 0100 00Dd 0010 0100 10Da 0010 0100 010d <#16 0010 0100 011a <#16 0010 1111 111D 0010 1110 111d 0011 0010 DnDm 1100 00Dm <#8.
....
....
...>
Arithmetic instructions ADD ADD Dn,Dm ADD imm4,Dm ADD imm8,Dm ADDC ADDW ADDC Dn,Dm ADDW DWn,DWm ADDW DWn,Am ADDW imm4,Am ADDW imm8,Am ADDW imm16,Am ADDW imm4,SP ADDW imm8,SP ADDW imm16,SP ADDW imm16,DWm ADDUW ADDUW Dn,Am
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Dm+DnDm Dm+sign(imm4)Dm Dm+imm8Dm Dm+Dn+CFDm DWm+DWnDWm Am+DWnAm Am+sign(imm4)Am Am+sign(imm8)Am Am+imm16Am SP+sign(imm4)SP SP+sign(imm8)SP SP+imm16SP DWm+imm16DWm Am+zero(Dn)Am Am+sign(Dn)Am Dm-DnDm Dn-DnDn Dm-imm8Dm Dm-Dn-CFDm DWm-DWnDWm Am-DWnAm DWm-imm16DWm Am-imm16Am DmDnDWk DWm/DnDWm-I...DWm-h Dm-Dn...PSW Dm-imm8...PSW mem8(abs8)-imm8...PSW mem8(abs12)-imm8...PSW mem8(abs16)-imm8...PSW DWm-DWn...PSW Am-DWn...PSW Am-An...PSW DWm-imm16...PSW Am-imm16...PSW 0 0 0 0 1 - - - - - - - - - - - -
3 3 4 3 3 3 3 5 7 3 4 7 7 3 3 3 2 5 3 3 3 7 7 3 3 3 4 6 7 9 3 3 3 6 6
2 2 2 2 3 3 2 3 4 2 2 4 4 3 3 2 1 3 2 3 3 4 4 8 9 2 2 3 3 5 3 3 3 3 3
61 6 61
...>
1 6
62 63 64 64 65 65 66 6 66 67 67 68 8 69 70 71 71 7 7
...> .... ...> .... .... .... .... ...> ...> .... ...>
ADDSW ADDSW Dn,Am SUB SUB Dn,Dm(when DnDm) SUB Dn,Dn SUB imm8,Dm SUBC SUBW SUBC Dn,Dm SUBW DWn,DWm SUBW DWn,Am SUBW imm16,DWm SUBW imm16,Am MULU DIVU CMP MULU Dn,Dm DIVU Dn,DWm CMP Dn,Dm CMP imm8,Dm CMP imm8,(abs8) CMP imm8,(abs12) CMP imm8,(abs16) CMPW CMPW DWn,DWm CMPW DWn,Am CMPW An,Am CMPW imm16,DWm CMPW imm16,Am Logical instructions AND AND Dn,Dm AND imm8,Dm AND imm8,PSW OR OR Dn,Dm OR imm8,Dm OR imm8,PSW XOR XOR Dn,Dm XOR imm8,Dm
...>
1
72 73 74 74
.... ....
.... ....
...> ...>
4 5
75 75 76 77 78
...> <#8. .... ...> ...> <#8. ...>
1 2
78 79 79 80 81 81 82 82 83
0000 0100 0000 0101 ...> ...> ...> ...> .... ....
...> <#8. ...>
.... ....
...> ...>
Dm&DnDm Dm&imm8Dm PSW&imm8PSW DmIDnDm DmIimm8Dm PSWIimm8PSW Dm^DnDm Dm^imm8Dm
0 0
0 0
3 4 5
2 2 3 2 2 3 2 3
84 84 85 86 86 87 9 88 88
0 0
0 0
3 4 5
0 0
0 0
3 5
Note: "Page" refers to the corresponding page in the Instruction Manual.
1 D=DWn, d=DWm 2 A=An, a=Am 3 d=DWm 4 D=DWk
5 D=DWm 6 #4 sign extended 7 #8 sign extended 8 Dn zero extended
9
mn
142
Instruction Set
Chapter 10 Appendices
MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size 3 3 2 2 Machine Code Notes Page
2
3
4
5
6
7
8
9
10
11
89 90
NOT ASR
NOT Dn ASR Dn
_ DnDn Dn.msbtemp,Dn.lsbCF Dn>>1Dn,tempDn.msb
0 0 -
0
0010 0010 10Dn 0010 0011 10Dn 0010 0011 11Dn 0010 0010 11Dn
LSR
LSR Dn
Dn.lsbCF,Dn>>1Dn 0Dn.msb
0
0
3
2
91 92
ROR
ROR Dn
Dn.Isbtemp,Dn>>1Dn CFDn.msb,tempCF
0
3
2
Bit manipulation instructions BSET BSET (io8)bp mem8(IOTOP+io8)&bpdata...PSW 0 1mem8(IOTOP+io8)bp BSET (abs8)bp mem8(abs8)&bpdata...PSW 1mem8(abs8)bp BSET (abs16)bp mem8(abs16)&bpdata...PSW 1mem8(abs16)bp BCLR BCLR (io8)bp mem8(IOTOP+io8)&bpdata...PSW 0 0mem8(IOTOP+io8)bp BCLR (abs8)bp mem8(abs8)&bpdata...PSW 0mem8(abs8)bp BCLR (abs16)bp mem8(abs16)&bpdata...PSW 0mem8(abs16)bp BTST BTST imm8,Dm BTST (abs16)bp Branch instructions Bcc BEQ label if(ZF=1), PC+3+d4(label)+HPC if(ZF=0), PC+3PC BEQ label
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0
5
5
0011 1000 0bp. ...>
93
0
0
4
4
1011 0bp. 0011 1100 0bp. .... ...>
93
0
0
7
6
94
0
5
5
95
0
0
4
4
1011 1bp. 0011 1100 1bp. .... ...>
1
95
0
0
7
6
....
...>
96
Dm&imm8...PSW mem8(abs16)&bpdata...PSW
0 0
0 0
5 7
3 5
97
0011 1101 0bp. 1000 1010 1000 1011 97
98
-
-
-
-
3
2/3
if(ZF=1), PC+4+d7(label)+HPC if(ZF=0), PC+4PC
-
-
-
-
4
2/3
2
98
BEQ label
if(ZF=1), PC+5+d11(label)+HPC - if(ZF=0), PC+5PC
-
-
-
5
2/3
...H
3
99
BNE label
if(ZF=0), PC+3+d4(label)+HPC - if(ZF=1), PC+3PC
-
-
-
3
2/3
1 100 2 100
BNE label
if(ZF=0), PC+4+d7(label)+HPC - if(ZF=1), PC+4PC
-
-
-
4
2/3
BNE label
if(ZF=0), PC+5+d11(label)+HPC - if(ZF=1), PC+5PC
-
-
-
5
2/3
...H
3 101 2 102
BGE label
if((VF^NF)=0),PC+4+d7(label)+HPC - if((VF^NF)=1),PC+4PC
-
-
-
4
2/3
BGE label
if((VF^NF)=0),PC+5+d11(label)+HPC - if((VF^NF)=1),PC+5PC
-
-
-
5
2/3
...H
3 102 2 103
BCC label
if(CF=0),PC+4+d7(label)+HPC - if(CF=1), PC+4PC
-
-
-
4
2/3
BCC label
if(CF=0), PC+5+d11(label)+HPC - if(CF=1), PC+5PC
-
-
-
5
2/3
...H
3 103 2 104
BCS label
if(CF=1),PC+4+d7(label)+HPC - if(CF=0), PC+4PC
-
-
-
4
2/3
BCS label
if(CF=1), PC+5+d11(label)+HPC - if(CF=0), PC+5PC
-
-
-
5
2/3
...H
3 104 2 105 3 105 2 106
BLT label
if((VF^NF)=1),PC+4+d7(label)+HPC - if((VF^NF)=0),PC+4PC
-
-
-
4
2/3
BLT label
if((VF^NF)=1),PC+5+d11(label)+HPC - if((VF^NF)=0),PC+5PC
-
-
-
5
2/3
1001 1110 .... ...H .... ...H
...H
BLE label
if((VF^NF)|ZF=1),PC+4+d7(label)+HPC - if((VF^NF)|ZF=0),PC+4PC
-
-
-
4
2/3
BLE label
if((VF^NF)|ZF=1),PC+5+d11(label)+HPC - if((VF^NF)|ZF=0),PC+5PC
-
-
-
5
2/3
...H
3 106 2 107
BGT label
if((VF^NF)|ZF=0),PC+5+d7(label)+HPC - if((VF^NF)|ZF=1),PC+5PC
-
-
-
5
3/4
Note: "Page" refers to the corresponding page in the Instruction Manual.
1 d4 sign extended 2 d7 sign extended 3 d11 sign extended
Instruction Set
143
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MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size 6 3/4 Machine Code Notes Page
2
3
4 .... ...H .... ...H .... ...H .... ...H .... ...H .... ...H ....
5 ...H
6
7
8
9
10
11
3 107 2 108
Bcc
BGT label
if((VF^NF)|ZF=0),PC+6+d11(label)+HPC - if((VF^NF)|ZF=1),PC+6PC
-
-
-
0010 0011 0001 1000 1001 BHI label
if(CFIZF=0),PC+5+d7(label)+HPC - if(CFIZF=1), PC+5PC
-
-
-
5
3/4
BHI label
if(CFIZF=0),PC+6+d11(label)+HPC - if(CFIZF=1), PC+6PC
-
-
6
3/4
...H
3 108 2 109
BLS label
if(CFIZF=1),PC+5+d7(label)+HPC - if(CFIZF=0), PC+5PC
-
-
-
5
3/4
BLS label
if(CFIZF=1),PC+6+d11(label)+HPC - if(CFIZF=0), PC+6PC
-
-
-
6
3/4
...H
3 109 2 110
BNC label
if(NF=0),PC+5+d7(label)+HPC - if(NF=1),PC+5PC
5
3/4
BNC label
if(NF=0),PC+6+d11(label)+HPC - if(NF=1),PC+6PC
-
-
-
6
3/4
...H
3 110 2 111
BNS label
if(NF=1),PC+5+d7(label)+HPC - if(NF=0),PC+5PC
-
-
-
5
3/4
BNS label
if(NF=1),PC+6+d11(label)+HPC - if(NF=0),PC+6PC
-
-
-
6
3/4
...H
3 111 2 112
BVC label
if(VF=0),PC+5+d7(label)+HPC - if(VF=1),PC+5PC
-
-
-
5
3/4
BVC label
if(VF=0),PC+6+d11(label)+HPC - if(VF=1),PC+6PC
-
-
-
6
3/4
...H
3 112 2 113
BVS label
if(VF=1),PC+5+d7(label)+HPC - if(VF=0),PC+5PC
-
-
-
5
3/4
BVS label
if(VF=1),PC+6+d11(label)+HPC - if(VF=0),PC+6PC
-
-
-
6
3/4
...H
3 113 1 114
BRA label BRA label BRA label
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PC+3+d4(label)+HPC PC+4+d7(label)+HPC PC+5+d11(label)+HPC if(Dm=imm8),PC+6+d7(label)+HPC / if(Dm=imm8),PC+6PC
- - -
- - -
- - -
- - -
3 4 5 6
3 3 3 3/4
...H .... ...> ...H ...H ...H 2 114 3 115 2 116 3 116 2 117 3 117 2 118 3 118 2 119
CBEQ
CBEQ imm8,Dm,label
CBEQ imm8,Dm,label
if(Dm=imm8),PC+8+d11(label)+H PC if(Dm=imm8),PC+8PC /
8
4/5
...> CBEQ imm8,(abs8),label
if(mem8(abs8)=imm8),PC+9+d7(label)+HPC if(mem8(abs8)=imm8),PC+9PC /
9
6/7
0010 1101 1100 <#8. 0010 1101 1101 <#8. 0011 1101 1100 .... ....
CBEQ imm8,(abs8),label
if(mem8(abs8)=imm8),PC+10+d11(label)+HPC if(mem8(abs8)=imm8),PC+10PC /
10 6/7
...> ...> <#8. <#8.
CBEQ imm8,(abs16),label if(mem8(abs16)=imm8),PC+11+d7(label)+HPC / if(mem8(abs16)=imm8),PC+11PC CBEQ imm8,(abs16),label if(mem8(abs16)=imm8),PC+12+d11(label)+HPC if(mem8(abs16)=imm8),PC+12PC / CBNE CBNE imm8,Dm,label if(Dm=imm8),PC+6+d7(label)+HPC / if(Dm=imm8),PC+6PC CBNE imm8,Dm,label if(Dm=imm8),PC+8+d11(label)+HPC / if(Dm=imm8),PC+8PC CBNE imm8,(abs8),label if(mem8(abs8)=imm8),PC+9+d7(label)+HPC / if(mem8(abs8)=imm8),PC+9PC CBNE imm8,(abs8),label if(mem8(abs8)=imm8),PC+10+d11(label)+HPC / if(mem8(abs8)=imm8),PC+10PC CBNE imm8,(abs16),label if(mem8(abs16)=imm8),PC+11+d7(label)+HPC / if(mem8(abs16)=imm8),PC+11PC CBNE imm8,(abs16),label if(mem8(abs16)=imm8),PC+12+d11(label)+HPC / if(mem8(abs16)=imm8),PC+12PC TBZ TBZ (abs8)bp,label TBZ (abs8)bp,label if(mem8(abs8)bp=0),PC+7+d7(label)+HPC 0 if(mem8(abs8)bp=1),PC+7PC if(mem8(abs8)bp=0),PC+8+d11(label)+HPC 0 if(mem8(abs8)bp=1),PC+8PC 0 0
11 7/8
12 7/8
...> 6
3/4
.... ...> ...H ...H 8
4/5
...> 3 119 2 120 3 120 2 121 3 121 2 122
9
6/7
0010 1101 1110 <#8. 0010 1101 1111 <#8. 0011 1101 1110 10 6/7
...> ...> ...H .... ...H <#8. <#8.
11 7/8
12 7/8
...> 7 8
6/7 6/7
0011 0000 0bp. 3 122
Note: "Page" refers to the corresponding page in the Instruction Manual.
1 d4 sign extended 2 d7 sign extended 3 d11 sign extended
144
Instruction Set
Chapter 10 Appendices
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2
3
4
5
6
7
8
9
10
11
1 123 2 123 1 124
TBZ
TBZ (io8)bp,label
if(mem8(IOTOP+io8)bp=0),PC+7+d7(label)+HPC 0 if(mem8(IOTOP+io8)bp=1),PC+7PC
0
7
6/7
0011 0100 0bp. ...>
...H .... ...> ...H TBZ (io8)bp,label TBZ (abs16)bp,label TBZ (abs16)bp,label
if(mem8(IOTOP+io8)bp=0),PC+8+d11(label)+HPC 0 if(mem8(IOTOP+io8)bp=1),PC+8PC if(mem8(abs16)bp=0),PC+9+d7(label)+HPC 0 if(mem8(abs16)bp=1),PC+9PC if(mem8(abs16)bp=0),PC+10+d11(label)+HPC 0 if(mem8(abs16)bp=1),PC+10PC
0 0 0
8 9
6/7 7/8
...> 0011 1110 0bp. 10 7/8
...> ...H 2 124 1 125 2 125 1 126 2 126
TBNZ
TBNZ (abs8)bp,label
if(mem8(abs8)bp=1),PC+7+d7(label)+HPC 0 if(mem8(abs8)bp=0),PC+7PC
0
7
6/7
0011 0001 0bp. TBNZ (abs8)bp,label TBNZ (io8)bp,label
if(mem8(abs8)bp=1),PC+8+d11(label)+HPC 0 if(mem8(abs8)bp=0),PC+8PC if(mem8(io)bp=1),PC+7+d7(label)+HPC 0 if(mem8(io)bp=0),PC+7PC
0 0
8 7
6/7 6/7
TBNZ (io8)bp,label
if(mem8(io)bp=1),PC+8+d11(label)+HPC 0 if(mem8(io)bp=0),PC+8PC
0
8
6/7
...> TBNZ (abs16)bp,label
if(mem8(abs16)bp=1),PC+9+d7(label)+HPC 0 if(mem8(abs16)bp=0),PC+9PC
0
9
7/8
0011 1111 0bp. ...H .... ...H
1 127 2 127
TBNZ (abs16)bp,label
if(mem8(abs16)bp=1),PC+10+d11(label)+HPC 0 if(mem8(abs16)bp=0),PC+10PC
0
10 7/8
...> JMP JSR
JMP (An) JMP label JSR (An)
0PC.17~16,An PC.15~0,0PC.H abs18(label)+HPC SP-3SP,(PC+3).bp7~0mem8(SP) (PC+3).bp15~8mem8(SP+1) (PC+3).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+3).bp17~16mem8(SP+2).bp1~0 0PC.bp17~16 AnPC.bp15~0,0PC.H
- - -
- - -
- - -
- - -
3 7 3
4 5 7
128
0011 1001 0aaH 0..>
5 128 129
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JSR label
SP-3SP,(PC+5).bp7~0mem8(SP) (PC+5).bp15~8mem8(SP+1) (PC+5).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+5).bp17~16mem8(SP+2).bp1~0 PC+5+d12(label)+HPC
-
-
-
-
5
6
0001 000H ....
...>
3 129
JSR label
SP-3SP,(PC+6).bp7~0mem8(SP) (PC+6).bp15~8mem8(SP+1) (PC+6).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+6).bp17~16mem8(SP+2).bp1~0 PC+6+d16(label)+HPC
-
-
-
-
6
7
0001 001H ....
....
...>
4 130
JSR label
SP-3SP,(PC+7).bp7~0mem8(SP) (PC+7).bp15~8mem8(SP+1) (PC+7).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+7).bp17~16mem8(SP+2).bp1~0 abs18(label)+HPC
-
-
-
-
7
8
0011 1001 1aaH 0..>
5 130
JSRV (tbl4)
SP-3SP,(PC+3).bp7~0mem8(SP) (PC+3).bp15~8mem8(SP+1) (PC+3).Hmem8(SP+2).bp7 0mem8(SP+2).bp6~2, (PC+3).bp17~16mem8(SP+2).bp1~0 mem8(x'004080+tbl4<<2)PC.bp7~0 mem8(x'004080+tbl4<<2+1)PC.bp15~8 mem8(x'004080+tbl4<<2+2).bp7PC.H mem8(x'004080+tbl4<<2+2).bp1~0 PC.bp17~16
-
-
-
-
3
9
1111 1110
131
NOP
NOP
PC+2PC
-
-
-
-
2
1
0000 0000
132
Note: "Page" refers to the corresponding page in the Instruction Manual.
1 d7 sign extended 2 d11 sign extended 3 d12 sign extended 4 d16 sign extended 5 aa=abs18.17 16
Instruction Set
145
Chapter 10 Appendices
Expand
Control instruction
Note: "Page" refers to the corresponding page in the Instruction Manual.
1
Number of repeats is 0 when imm3=0.
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Ver2.0(1997.9.26)
146
Instruction Set
Chapter 10 Appendices
8-3 Instruction Map
1st nibble\2nd nibble
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Extension code: b'0010' 2nd nibble\3rd nibble
Instruction Map
147
Chapter 10 Appendices
Extension code: b'0011' 2nd nibble\3rd nibble
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Ver2.0(1997.9.26)
148
Instruction Map
Chapter 10 Appendices
8-4 Summary of Special Function Registers
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Summary of Special Function Registers
149
Chapter 10 Appendices
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150
Summary of Special Function Registers
Chapter 10 Appendices
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Summary of Special Function Registers
151
Chapter 10 Appendices
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152
Summary of Special Function Registers
Chapter 10 Appendices
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Summary of Special Function Registers
153
Chapter 10 Appendices
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154
Summary of Special Function Registers
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MN101C115 / 117 LSI User's Manual
August,1999 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electronics Corporation
(c) Matsushita Electric Industrial Co., Ltd. (c) Matsushita Electronics Corporation
Semiconductor Company Matsushita Electronics Corporation
Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.mec.panasonic.co.jp
SALES OFFICES
s U.S.A. SALES OFFICE
Panasonic Industrial Company [PIC] q New Jersey Office: 2 Panasonic Way, Secaucus, New Jersey 07094 Tel: 201-392-6173 Fax: 201-392-4652 q Milpitas Office: 1600 McCandless Drive, Milpitas, California 95035 Tel: 408-945-5630 Fax: 408-946-9063 q Chicago Office: 1707 N. Randall Road, Elgin, Illinois 60123-7847 Tel: 847-468-5829 Fax: 847-468-5725 q Atlanta Office: 1225 Northbrook Parkway, Suite 1-151, Suwanee, Georgia 30174 Tel: 770-338-6940 Fax: 770-338-6849 q San Diego Office: 9444 Balboa Avenue, Suite 185 San Diego, California 92123 Tel: 619-503-2940 Fax: 619-715-5545
s HONG KONG SALES OFFICE
Panasonic Shun Hing Industrial Sales (Hong Kong) Co., Ltd. [PSI(HK)] 11/F, Great Eagle Centre, 23 Harbour Road, Wanchai, Hong Kong. Tel: 2529-7322 Fax: 2865-3697
s TAIWAN SALES OFFICE
Panasonic Industrial Sales Taiwan Co.,Ltd. [PIST] q Head Office: 6th Floor, Tai Ping & First Building No.550. Sec.4, Chung Hsiao E. Rd. Taipei 10516 Tel: 2-2757-1900 Fax: 2-2757-1906 q Kaohsiung Office: 6th Floor, Hsien 1st Road Kaohsiung Tel: 7-223-5815 Fax: 7-224-8362
s SINGAPORE SALES OFFICE
Panasonic Semiconductor of South Asia 300 Beach Road # 16-01 The Concourse Singapore 199555 Tel: 390-3688 Fax: 390-3689 [PSSA]
s CANADA SALES OFFICE
www..com
Panasonic Canada Inc. [PCI] 5700 Ambler Drive Mississauga, Ontario, L4W 2T3 Tel: 905-624-5010 Fax: 905-624-9880
s MALAYSIA SALES OFFICE
Panasonic Industrial Company (Malaysia) Sdn. Bhd. q Head Office: [PICM] Tingkat 16B Menara PKNS PJ No.17,Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel: 03-7516606 Fax: 03-7516666 q Penang Office: Suite 20-17,MWE PLAZA No.8,Lebuh Farquhar,10200 Penang Malaysia Tel: 04-2625550 Fax: 04-2619989 q Johore Sales Office: 39-01 Jaran Sri Perkasa 2/1,Taman Tampoi Utama,Tampoi 81200 Johor Bahru,Johor Malaysia Tel: 07-241-3822 Fax: 07-241-3996
s GERMANY SALES OFFICE
Panasonic Industrial Europe G.m.b.H. q Munich Office: Hans-Pinsel-Strasse 2 85540 Haar Tel: 89-46159-156 Fax: 89-46159-195 [PIEG]
s U.K. SALES OFFICE
Panasonic Industrial Europe Ltd. [PIEL] q Electric component Group: Willoughby Road, Bracknell, Berkshire RG12 8FP Tel: 1344-85-3773 Fax: 1344-85-3853
s FRANCE SALES OFFICE
Panasonic Industrial Europe G.m.b.H. q Paris Office: 270, Avenue de President Wilson 93218 La Plaine Saint-Denis Cedex Tel: 14946-4413 Fax: 14946-0007 [PIEG]
s CHINA SALES OFFICE
Panasonic SH Industrial Sales (Shenzhen) Co., Ltd. [PSI(SZ)] 7A-107, International Business & Exhibition Centre, Futian Free Trade Zone, Shenzhen 518048 Tel: 755-359-8500 Fax: 755-359-8516 Panasonic Industrial (Shanghai) Co., Ltd. [PICS] 1F, Block A, Development Mansion, 51 Ri Jing Street, Wai Gao Qiao Free Trade Zone, Shanghai 200137 Tel: 21-5866-6114 Fax: 21-5866-8000
s ITALY SALES OFFICE
Panasonic Industrial Europe G.m.b.H. q Milano Office: Via Lucini N19, 20125 Milano Tel: 2678-8266 Fax: 2668-8207 [PIEG]
s THAILAND SALES OFFICE
Panasonic Industrial (Thailand) Ltd. [PICT] 252/133 Muang Thai-Phatra Complex Building,31st Fl.Rachadaphisek Rd.,Huaykwang,Bangkok 10320 Tel: 02-6933407 Fax: 02-6933423 080499
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